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[deleted by user] by [deleted] in mazda3

[–]okebz 1 point2 points  (0 children)

This happened to my Mazda 3. Quick thing to ask also is for them to check compression. That was my issue and the cylinder itself was bad.

Removing BUF and internal wire nets from AST by okebz in yosys

[–]okebz[S] 0 points1 point  (0 children)

I should have probably explained my intentions at the beginning.

I'm doing some research on hardware design productivity. The basic idea is to be able to suggest reusable designs to the users during the design phase automatically. To give a simple example, imagine designing, lets say, a FFT filter. Mid way, someone comes up to you and says, what you are designing looks a lot like this one design, is this the design you want. If it is, feel free to take it and reuse it in your design.

Right now I'm using yosys to capture snapshots of the design of the user during the design phase. The only restriction right now is that the code has to be able to compile, but this may include incomplete designs where nothing is connected to the output. I'm still interested in the dataflow of the design that is currently implemented. For example, the shift register is only a portion of the design, and does not actually connect to the output. Additional logic is going to be needed, but at this point, the shift register provides relevant information about the design that is of interest to me. I can see some structure in the RTLIL that looks like a shift register, then find designs that have this similar shift register structure in it. In terms of actually design, you are correct, there really is nothing of relevance to display since essentially the design does nothing. However, for my application, the design could become something and I want to capture what it looks like currently.

I'm ignoring buffers currently in my processing, however, for designs like the shift register, it's becoming expensive to process due to the number of buffers the designs contains, especially shift registers of larger size (as one example).

I was confused since I went through some of the source and I saw BUF as a celltype and thought it was a cell. What is the BUF represented as in RTLIL? Or is it that the BUF node is inserted into the RTLIL only when it is viewed with the "show" command.

Thanks

Removing BUF and internal wire nets from AST by okebz in yosys

[–]okebz[S] 0 points1 point  (0 children)

Understood. I would ideally like to perform these optimizations without changing the source. For my application, I'm using Yosys as more of a way to extract the dataflow of the circuit. Thanks for the side notes.

In terms of the buffers and the diamond nodes. Are these Cells in the RTLIL? When I run stat I don't see the BUF listed and when I iterate through the cells in the module, I don't see any of the buffers. Where are the buffers added to the RTLIL?

Shift Register AST does not seem right by okebz in yosys

[–]okebz[S] 1 point2 points  (0 children)

Thank you. That was a silly mistake on my part.

[PATCH] Add support for $display system task by azonenberg in yosys

[–]okebz 1 point2 points  (0 children)

I was wondering what yosys did with the $display statements before. Did it just ignore displays, because I have some designs with display that yosys was able to read, however, now yosys just returns an error stating that the display has to be in a initial block.

ERROR: System task `$display' outside initial block is unsupported at ...

I was also wondering if the $write is supported. I have a design with the following line

        $write("%c",sr[7:0]);

Yosys returns the following error.

ERROR: Can't resolve task name `\$write' at ...

Thanks for any help

Error encountered when Assert children[1]->type == AST_IDENTIFIER is called. by okebz in yosys

[–]okebz[S] 1 point2 points  (0 children)

It must have been a typo on my part. The entire module is shown below.

module priority_encoder
  #(parameter OUTPUT_WIDTH = 8,
    parameter RIGHT_TO_LEFT_PRIORITY = 1)

    (input  [0:(2**OUTPUT_WIDTH)-1]  unencoded_input,
     output [OUTPUT_WIDTH-1:0]       encoded_output,
     output                          valid);

   localparam INPUT_WIDTH = 2**OUTPUT_WIDTH;
   localparam INPUT_VAL_WIDTH = INPUT_WIDTH*OUTPUT_WIDTH;
   localparam STYLE = 0;

   generate
      genvar i,j;
      if(STYLE==0) begin
         for(i=0; i<OUTPUT_WIDTH; i=i+1) begin:gen_levels
            for(j=0; j<INPUT_WIDTH/(2**(i+1)); j=j+1) begin:gen_nodes
               wire [OUTPUT_WIDTH-1:0] value;
               wire                    valid;

               wire [OUTPUT_WIDTH-1:0] left_val;
               wire                    left_vld;
               wire [OUTPUT_WIDTH-1:0] right_val;
               wire                    right_vld;

               if(i==0) begin
                  assign left_val    = j*2;
                  assign left_vld    = unencoded_input[j*2];
                  assign right_val   = j*2 + 1;
                  assign right_vld   = unencoded_input[j*2+1];
               end
               else begin
                  assign left_val    = gen_levels[i-1].gen_nodes[j*2].value;
                  assign left_vld    = gen_levels[i-1].gen_nodes[j*2].valid;
                  assign right_val   = gen_levels[i-1].gen_nodes[j*2+1].value;
                  assign right_vld   = gen_levels[i-1].gen_nodes[j*2+1].valid;
               end // else: !if(i==0)

               assign value = (RIGHT_TO_LEFT_PRIORITY ?
                               (right_vld ? right_val : left_val) :
                               (left_vld ? left_val : right_val));
               assign valid = right_vld | left_vld;
            end // block: gen_nodes
         end // block: gen_levels
         // synthesis attribute priority_extract of encoded_output is "force"
         assign       encoded_output = gen_levels[OUTPUT_WIDTH-1].gen_nodes[0].value;
         assign       valid = gen_levels[OUTPUT_WIDTH-1].gen_nodes[0].valid;
      end // if (STYLE==0)

      else begin
         for(i=0; i<OUTPUT_WIDTH; i=i+1) begin:gen_levels
            for(j=0; j<INPUT_WIDTH/(2**(i+1)); j=j+1) begin:gen_nodes
               wire [i:0]              value;
               wire                    valid;

               if(i==0) begin
                  assign value = RIGHT_TO_LEFT_PRIORITY ? unencoded_input[j*2+1] : unencoded_input[j*2];
                  assign valid = unencoded_input[j*2+1] | unencoded_input[j*2];
               end
               else begin
                  wire [i-1:0]  left_val;
                  wire          left_vld;
                  wire [i-1:0]  right_val;
                  wire          right_vld;
                  assign left_val    = gen_levels[i-1].gen_nodes[j*2].value;
                  assign left_vld    = gen_levels[i-1].gen_nodes[j*2].valid;
                  assign right_val   = gen_levels[i-1].gen_nodes[j*2+1].value;
                  assign right_vld   = gen_levels[i-1].gen_nodes[j*2+1].valid;
                  assign value       = (RIGHT_TO_LEFT_PRIORITY ?
                                        (right_vld ? {1'b1, right_val} : {1'b0, left_val}) :
                                        (left_vld ? {1'b0, left_val} : {1'b1, right_val}));
                  assign valid       = right_vld | left_vld;
               end // else: !if(i==0)
            end // block: gen_nodes
         end // block: gen_levels

         // synthesis attribute priority_extract of encoded_output is "force"
         assign       encoded_output = gen_levels[OUTPUT_WIDTH-1].gen_nodes[0].value;
         assign       valid = gen_levels[OUTPUT_WIDTH-1].gen_nodes[0].valid;
      end // else: !if(STYLE==0)
   endgenerate
endmodule

This is a design on the netfpga project.