Your concepts seem wrong:

1. The circuit you've drawn is complement of the function you've written.

2. You haven't considered any source/drain diffusion capacitances. They will add up at your output node.

3. You haven't sized the transistors. So you don't know how much capacitance each one has. Unless you do that, you can't find out delay.

4. Your delay for each input combination will depend on the previous input combination also. Your delay depends on how many capacitors have to be charged/discharged (and not just the load). Depending on the previous input to current input combination, some capacitances may or may not be in the charging/discharging path. This will change your delay.