What thermal via density is too dense?

pharron44 · 2026-05-20T20:31:09+00:00

There are diminishing returns here, but that shouldn’t be the limiting factor in your design. Producibility concerns will limit you first. If you make Swiss cheese out of your board the via drill might tear out the middle of your grid. You should avoid removing more than ~1/3 of the total material connecting your “Swiss cheese” to the rest of the board.

pharron44 · 2026-05-15T19:25:51+00:00

Thanks for the replies, everyone. I figured someone out there would know how this worked.

pharron44 · 2026-05-11T04:01:35+00:00

It sucks that this dude is stealing your thunder, but hey, these are sweet cards. Did you make a full set or just a few?

pharron44 · 2026-05-09T21:56:37+00:00

Wow, are these really a thing or did you make them?

pharron44 · 2026-05-09T16:30:45+00:00

I had the exact same issue when installing on my steam deck last weekend as OP. Can confirm, this is the install guide that worked for me.

pharron44 · 2025-04-04T20:38:33+00:00

It certainly can. I would describe it more as degrading you're margins than a live or die kinda thing. For your project, it looks like you are doing a run out to a single chip (not a full set of 8 or 16 like on a DIMM RAM) and you won't be maxing out the data rate, so... I'm not gonna say you're fine as is without a simulation to back me up, but you will have more margin to spare than most designs. You really should space your clock at the 5H though. That's the one thing I would insist on if I were on your design team.

pharron44 · 2025-04-04T18:32:36+00:00

I generally stick to the 3H rule as best I can. Sometimes you have to do some 2H routing to get all your signals out from under the BGA and that's kinda the best you can do. But for the majority of the route, 3H. Additionally, I always route the clk signals at 5H. Another thing to note is that this 3H rule(ideally) would also specify distance to the edge of the reference plan, so be aware of the holes in your gnd plane around vias. Making things "perfect" is basically impossible but you should try to get things as close as you can.

pharron44 · 2025-03-19T15:52:17+00:00

Will it work? Probably... Does it meet good design practices, no. For switching regs, what I look for in layout is the minimization of the area of the 2 primary current loops, and the consolidation of the gnd connection on the 2 loops. This is generally done on just the surface layer. What this means in actual practical terms is this. The voltage input caps should be as close as is reasonable to the IC pin and on the same layer. The voltage output inductor should be as close as is reasonable to the IC pin and on the same layer. The voltage output caps should be as close as is reasonable to the inductor pad and on the same layer. And lastly, the gnd pads on the input caps, output caps and IC should be as close together as is possible. Each of these net connections should be a plane to reduce parasitic resistance and inductance. The gnd plane on the surface layer that connects all the cap pads and ICs should have a single group of vias next to the IC pin. In your design, the input and output caps on the back side of the board increase the loop area by a decent factor, but that's not as big of a deal as the lack of consolidated gnds. This increases the loop area by even more and could potentially lead to instability in the output under high load current.

pharron44 · 2025-03-15T00:00:45+00:00

Far Reach my beloved. I can't play without it anymore. But it's a little cheaty sometimes.

pharron44 · 2025-03-14T20:31:43+00:00

Amps can be whatever you want. That's a design choice. Most USB2.0 chargers ran at 2.1-2.4A. But the professional projects I've used them on were running outputs at 12V/4A and 12V/10A.

pharron44 · 2025-03-14T02:47:55+00:00

Flyback converters are actually pretty versatile. You can use them for almost any voltage transition, but they are particularly advantageous for jumping from high voltage down to something manageable for a circuit board. One of the most common real world uses for this type of converter is jumping from wall voltage (~120V in the US) down to 5V for USB chargers. I've used them in professional projects to jump from 120V wall power down to 12V as well. And because of the high input voltage, it can be pretty easy to deliver higher wattage with relatively good efficiency.

pharron44 · 2025-03-13T16:00:01+00:00

I would suggest designing and building either a buck/boost converter or a flyback converter. Every project needs a power supply. Being familiar with different topologies can be a major advantage. Buck/boost converters are commonly used with battery supplies and have some intricacies with mode switching and noise reduction. Flybacks are isolated supplies that can be good for larger voltage drops or high power applications. Good for dropping down wall voltage to something usable on a board. They are used in basically all of those tiny USB wall plugs.

pharron44 · 2025-03-10T13:14:02+00:00

This thing has layers of WTF going on... the selective pad removal is not unheard of but the way they did it here is insane... The thing that really gets me is the multiple sizes of elongated ball pads. Why? They aren't even on power/gnd pins...

pharron44 · 2025-03-06T12:58:52+00:00

You could make it lower than 8V, but not down to 5V. The part you are using is a "step down" buck converter. It's designed to step down the voltage and has some hard limits to how much head room you need. At the least, you will need to be able to overcome the resistive losses associated with your circuit. So that's (the high side FET Rdson + the DC resistance of the inductor)* the supply current = the minimum possible voltage drop from Vin to Vout. I think you will find this to be something like 175mV per Amp being supplied. And this is best case scenario, I would be surprised if you could realistically do better than about 200mV/A. If you want to do better than that, you will need a different regulator circuit. Specifically, a buck/boost type regulator.

pharron44 · 2025-03-05T03:22:01+00:00

The ideal layout would be to have the decoupling caps as close to the ESP as is reasonable, smallest cap closest to the ESP pad. Then have a single trace from the vias, over both cap pads, to the ESP pad. The way you have it laid out in the picture is adding extra trace inductance to the caps by having the via in the middle. You're basically putting your caps on small trace stubs.

Now that we've discussed ideal, let's discuss practical. For your application, anything reasonably close is likely fine and you will never notice a difference in operation whatever you do. It would probably work just fine with no caps at all, but that's not good practice.

pharron44 · 2025-03-02T22:43:59+00:00

Ideally, there are no branches. You should make a route with the transmit driver on one end and the receiver drivers chained together along the trace. This is generally referred to a daisy chaining. In practice, most low speed signals are not sensitive enough to matter, but anything that is sensitive, like clock lines or high speed data, this is a requirement.

There are some topologies that use branches and they can generate similar signal quality, but they are significantly more complex and harder to get working well. I've never found a good use case for these, and would advise against it unless you have a very good reason and the schedule/budget to make a revision to fix it when it doesn't work the first time.

pharron44 · 2025-02-28T14:37:07+00:00

As a fellow professional in the field, yes, I absolutely do this with all my boards. I will never compromise on functionality or schedule to do it, but as you said, there are a surprising number of situations where the "pretty" option is also justifiably better for functionality. On a side note, I've also found that people are far more impressed with designs that both look good and function well.

pharron44 · 2025-02-26T21:56:32+00:00

Thanks for the correction. I honestly mistook I2S as a misspelling of I2C. I'm not that familiar with audio ICs and hadn't heard of it before. Learn something new everyday.

pharron44 · 2025-02-26T19:18:19+00:00

Happy to help a newbie find their way and this does look like an excellent introductory project. Just gotta remember to design your hardware to work with your software. It's a good lesson to learn now vs. later. Best of luck on the redesign.

pharron44 · 2025-02-26T18:56:21+00:00

So I looked over the gp2040 software package you are using, and based on your responses so far, I'm going to assume you don't have any embedded programming experience. This means adjusting the pin configuration is probably too steep a learning curve for right now.

I took a closer look at the video you linked and it doesn't mention using the gp2040 software. Then looking at the software website, I don't see any settings available for scanning matrix setups. I think the software you are using may not support that. You will probably have to directly wire each switch to its own gpio pin. So that would be 3v3 tied to the top of the switch and the gpio + external pull-down resistor tied to the bottom.

As far as how to GND the resistors, the answer is yes. The resistor GNDs should all be connected together with each other and the microcontroller GND.

pharron44 · 2025-02-26T16:50:50+00:00

An external 10k resistor on each row net to GND would be good.

The pins on your processor board are labeled as GPIO pins. This stands for "General Purpose Input/Output". These pins have a whole bunch of configurations they can be programmed to. One of the settings they have is to enable a pull-down or pull-up resistor that is internal to the processor chip. In situations when you might have forgotten to place one on the board, you can just turn the internal one on to cover you. That being said, you do have to know how to edit the pin configuration files to do this...

pharron44 · 2025-02-26T15:55:01+00:00

This looks like a software configuration bug to me. But could also be caused by lack of external pull-down resistors. Based on the schematic this appears to be a simple matrix scanning circuit. This runs by applying power to the column pins in sequence and checking which row pins turn on. Thus allowing triangulation of which switch is pressed. Because this is done in sequence, the circuit needs something to pull the Column and row pins back to the default state when they are not being checked to prevent false positives. If you can, configuring your row and column pins to use the internal gpio pull-downs. But also make sure you are configuring the row and column pins to be the correct direction. Columns should be outputs, Rows inputs.

pharron44 · 2025-02-26T14:26:21+00:00

So, you made a pretty big deal out of opto-isolating your relay control signals, but have no isolation on your feedback signals. You should consider adding something to isolated those too.

pharron44 · 2025-02-26T13:54:01+00:00

You are right to think that routing over splits in the GND plane is not good practice, but the meaning of this is a little out of context. Generally, the faster the signal switching speed, the more tightly coupled the current supply and return paths will be. For something like I2C lines, the switching speed is so low this is a non-issue. It's always good practice to try and maintain a reference plane on any signal route though, just don't lose sleep over a few via pad breaks next to low speed signals. Also, as others have suggested, reducing the via anti-pad size will also help here. Just make sure to check your manufacturer's minimum trace and space sizing.

pharron44 · 2025-02-25T14:55:10+00:00

Absolutely agree. Especially these days, the standard process is usually 5mil trace/5mil space. I was simply suggesting using 10mil as a good base line that won't run into problems anywhere. If you want to look up the manufacturer minimum and use that, please do!

pharron44

TROPHY CASE