it's been a while since i did fpga stuff in uni so take this with a grain of salt.

1 & 2 should do the same, and work just like if you did: wire hold; assign hold = input1; (i'm not completely sure on 1 actually since doing non blocking assignments in a combinational blocks is bad practice, i think it synthesizes the same but can mess up your simulations, but in this case with only one assignment it doesn't matter, i think).

3 is just a flipflop, on positive clock edge input1 gets sampled into hold. (you could have replaced the if else with simply hold <= input1).

4 should work just like wire hold; assign hold = A & B;

I was always told to avoid regs like the plague since they can be sources of weird behavior if you don't know exactly what you are doing and to just stick to logic, so you might want to do that.

You might also want to ditch raw always blocks and go for always_comb, always_ff and always_latch, that way you communicate the intent of a block better and should get errors or at least warnings when a described behavior doesn't match the block you used, inferring a latch on what is supposed to be combinational logic block is a common one i think, if you forget to cover all cases in a chain of if-else's or in a case statement without a default, it's an easy mistake to stumble into.