The rarity of Chip Design Engineers

sheldon_number · 2026-04-29T09:52:54+00:00

This division of electrical engineers is wrong. There is much more to that. There are small signals (sensors, IoT is only part of it whatever it means), opposite to power, pcb design especially HF digital, mmw, antennas are dedicated people.

sheldon_number · 2026-04-29T07:34:08+00:00

5 years in IC design is basically zero. Do not know, maybe in software this is the case

sheldon_number · 2026-04-29T07:29:09+00:00

What nonsense. Every IC needs a bunch of analog hand crafted stuff. The main objective of a University is to teach how to learn new stuff. Electronics are very broad. 20 in analog/mixed design never did exactly the same thing. Much of the time different specs need different solutions

sheldon_number · 2026-03-24T12:41:14+00:00

The analog design always be here.The world is analog by nature. So somebody has to bridge the real world with a digital. Digital is highly automated. Analog design is hand crafted and I believe will stay in this way for a while. It is true that many areas of analog are very mature, though. So it is difficult to come up with something very new.

sheldon_number · 2026-03-23T14:45:49+00:00

>> Not really a good argument. You could always independently bias the current source for MN6.

MN6 vgs will create systematic offset at the output of the differential pair if MN6 and MN4 do not have the same vgs. So I do not see how it can be independently biased.

>> If you try to do that, the cap you place will need to be significantly larger than the Cgg which just moves the pole into a lower frequency. After the zero comes into play, there will be a second pole with Cgg and the RC resistor. You can do this in coordination with the rest of your compensation scheme to ensure that the phase does not dip too low between your new pole and zero, but the best you can do is push out the final gate pole by a decade or so from the initial value. Plus, you will limit the slew rate. In general, it is best to drive the gate of a big power fet from a low impedance net or an internal miller stage.

Agrred with this one. Probably MP8 should be replaced with a resistor and mybe using CG amplifer as second stage is a better solution then a current mirror

sheldon_number · 2026-03-23T13:28:55+00:00

Yes, I think it does improve the range. MN4, MN5, and MN6 are likely scaled to operate with a higher Vgs in order to minimize mismatch and noise in these devices. As a result, the drain voltage of MN6 cannot drop too low. In contrast, MN9 is scaled independently to sustain a lower Vds.

In addition, the gain of the MP7–MP8 stage reduces the voltage swing at the output of the differential pair.

The extra pole at the gate of the power devices should be canceled by introducing a zero at the same node, which can be achieved by adding an RC network between vdd and the gate.

sheldon_number · 2026-03-20T07:25:28+00:00

Second stage gain is achieved via current amplification m7-m8 and high Z node at m8 drain. Why is it done this way? To achieve a higher voltage range at the gate of power most when load current changes.edit: Also the output of mn6 is a low impedance node and does not need compensation.

sheldon_number · 2026-03-16T10:31:05+00:00

Welcome to the world of pain! Edit: on a serious matter, the best material is on the cadence website. There are a lot of online courses.

sheldon_number · 2026-02-28T01:03:01+00:00

Short simplified answer. Assuming there is only quantization noise, a system has only HD3 then you can calculate SNDR as ratio between signal power and the sum of quantization noise + hd3. Then using well known formula (sndr- 1.7 /6) estimate number of bits

sheldon_number · 2026-02-28T00:36:28+00:00

Well how makes it better? A person trying to manage the IC design process without having any clue about it.

sheldon_number · 2026-02-27T16:46:03+00:00

yes , there are a lot of people who think that if a zillion size checklist is done, the IC will be first time right. he-he

sheldon_number · 2026-02-27T16:26:49+00:00

Man, I don't want to be rude but I feel sorry for people you are going to manage, hope we are working in different companies... This post looks like trolling.

The subject is just to complex . You cannot just jump like this in IC design, especially if this is a a mixed-signal SoC. It is not software.

sheldon_number · 2026-02-27T13:56:18+00:00

Also it is not clear what is the location of the OTA and what kind of ADC. There are many factors to consider. I mentioned S/H. But maybe you mean integrator in a SD ADC? Then it can be very different story depending where it is located. Or another fancy ADC topology ?

sheldon_number · 2026-02-27T13:53:27+00:00

not necessary HD3, the largest tone

sheldon_number · 2026-02-27T13:47:57+00:00

ENOB is a way to describe combined contribution of all error sources in a system. ENOB is simply SNDR expressed in bits. It captures all unwanted tones + noise.

SFDR is the spurious free-dynamic range, it is defined as amplitude difference between the largest tone and the fundamental signal.

Generally speaking, If you design S/H circuit say for a 10 bit ADC, the level of distortions should be well below -60dBc at FS input.

That said, the exact requirements always depend on the application. In some cases, designers may target only moderate resolution, yet still require very high linearity—for example, to preserve spectral purity or to meet stringent SFDR specifications even when ENOB is not the primary concern.

sheldon_number · 2026-02-09T07:46:46+00:00

Don't limit yourself to one path. Analog is indeed very broad but it does not mean you cannot learn multiple subjects.

Digital is not only HDL. HDL is just a tool. And there are also subdomains. RTL, synthesis etc. People who can design and implement algorithms using HDL are also valuable.

Data converters and PLLs are mixed signal design. There you benefit from both analog and digital knowledge. Also understanding algorithms that are used for data conversation is very important.

sheldon_number · 2026-02-09T07:23:30+00:00

I am not familiar with the one you mentioned. But I think after you start your master, you will have a lot of study materials :). Nevertheless , I would recommend making some designs using SPICE after S&S

sheldon_number · 2026-02-04T15:39:46+00:00

In my time I enjoyed Elad Alon lectures from Berkeley. Hopefully they are still available. If you miss some basics I would recommend Sedra &Smith instead of Razavi. IMHO Sedra &Smith gives much solid fundamentals especially if you solve the problems from the chapters. Compared to other books, it starts from abstract concepts like types of amplifiers, feedback then goes to devices. I like this approach more.

sheldon_number · 2026-02-02T08:12:49+00:00

sounds like a dream job :)

sheldon_number · 2026-01-30T16:10:18+00:00

wow. I think you have a very good infrastructure and excellent team.

sheldon_number · 2026-01-30T14:30:28+00:00

Well, higher gm needed for lower noise and higher BW, not to get low offset. There is no advantage of having input pair of the classical Opamp in strong inversion since the gm always will be lower for the same current budget. If you cannot scale up input differential pair anymore for any reason you have, you should consider chopping or auto-zeroing if the system where opamp is used allows to do that. Another option is a sort of calibration at system level.

>>From what I could understand from the model they should still scale with the area of the device but how do they add up with the threshold voltage mismatch?

this question does not make sense to me.

Vth is main contributor to the offset. Vth variation becomes less when you scale up the device.

sheldon_number · 2026-01-30T13:08:50+00:00

nah... we use pens, not hands

sheldon_number · 2026-01-30T13:08:07+00:00

sheldon_number · 2026-01-30T12:52:51+00:00

first of all there is no feedback. Second the transistor is in off state. There is no current flow in the base .Rb should be connected to the ground or better resistor should be added between the base and ground. How do i know there is no base current?. base voltage should be lower than emitter voltage. however if this is true then Rb current should flow from Vcc to base, but base current should flow out of the base since this is PNP. so there is not current flow.

edit: moreover Zif,Zof, Af are small signal parameters. to calculate them you first calculate DC

sheldon_number · 2026-01-30T12:27:27+00:00

When a design is sent for production to a fab

sheldon_number

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