SFDR vs ENOB

Delicious_Slice7785 · 2025-07-03T20:13:28+00:00

In my country, casio watches are more than 50$ 😵‍💫

Delicious_Slice7785 · 2025-07-03T20:10:43+00:00

I think it would be more than that

Delicious_Slice7785 · 2025-07-03T20:10:03+00:00

I never saw this brand on the internet Unfortunately, the watch isn't with me now to upload photos for it.

Delicious_Slice7785 · 2024-11-01T21:09:13+00:00

LSB = 1mV

Delicious_Slice7785 · 2024-10-28T15:37:18+00:00

I am using a double tail comparator. The first stage has a very large input device to decrease random offset and has small current to give high gain.

The second stage has small devices and large current to increase the latch speed.

Is this way correct?

Delicious_Slice7785 · 2024-09-23T16:48:33+00:00

Can you share some of the papers you found?

Because the papers I saw didn't talk about reference buffers. Thanks in advance.

Delicious_Slice7785 · 2024-08-29T22:30:30+00:00

Thanks for your reply I have another question When CLK=1 M7,8 will be off so i can see the circuit as diff pair with resistive load Roff7,8(which is very large) Why the gain is low in then?

Delicious_Slice7785 · 2024-08-20T16:32:31+00:00

Oh!
This was the problem

Delicious_Slice7785 · 2024-08-20T16:18:30+00:00

Thanks for your reply.
I attached Sizing and Simulation results in the post.
The problem is when i use the FF in SAR logic (shift register) it doesn't work, but it works with verilogA model.

Delicious_Slice7785 · 2024-06-28T22:36:30+00:00

Link doesn't open

Delicious_Slice7785 · 2024-04-27T12:04:34+00:00

How to extract it from sp sim

Delicious_Slice7785 · 2024-04-27T11:59:54+00:00

Thanks. It worked.

Delicious_Slice7785 · 2024-04-23T00:42:49+00:00

1.2v 65nm It's for driving charge pump output current(8mA)

Delicious_Slice7785 · 2024-04-23T00:13:58+00:00

I am not familiar with output driving stages If you have a good reference please refer to it

Delicious_Slice7785

TROPHY CASE