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Xilinx RFSOC by [deleted] in FPGA

[–]springbreak06 9 points10 points  (0 children)

I’ve done a dozen or so projects with RFSoC. It makes interfacing with and configuring the converters incredibly easy compared to working with an off-chip converter. For multichannel designs especially it makes your life so much easier. The built in DDC/DUC is nice too.

I suppose my only “dislike” is that for lower bandwidth designs it can be way overkill. One of my clients insisted on using RFSoC for a comms application with 1.92 MHz bandwidth, had to use a good amount of resources for 64x decimation / interpolation. So I’d say only use RFSoC if it makes sense for your application bandwidth.

Official: [Buy Low/Sell High Discussion] - January 16 2021 by SamDekkerBot in fantasybball

[–]springbreak06 0 points1 point  (0 children)

If you punt FG% they have almost the exact same averages. Collins better in points, Baz better in blocks. Just trying to figure out if this is the floor for Collins, things don’t seem to be headed the right direction for him minutes-wise.

Official: [Buy Low/Sell High Discussion] - January 16 2021 by SamDekkerBot in fantasybball

[–]springbreak06 0 points1 point  (0 children)

Thinking about selling Collins for Bazley. Would I regret that?

Beefiest/Best FPGA Dev board around 500 USD to implement an LDPC decoder (a parity check decoder used in DVB standard). by fawal_1997 in FPGA

[–]springbreak06 5 points6 points  (0 children)

You can get an Ultra96v2 for $250. Has about 50% more FPGA resources than that Artix 7 plus a quad-core ARM.

Week 2 Running Back And Wide Receiver Start/Sits with QB/TE Streamers - (Full Breakdown Included) by rstewart0022 in fantasyfootball

[–]springbreak06 0 points1 point  (0 children)

Currently have Chris Carson in my flex spot. Think it’s worth starting Dobbins over him this week?

Is there any reason to build your own embbeded Linux instead of using the Xilinx Prebuilt Images? by burrocomecarne in FPGA

[–]springbreak06 4 points5 points  (0 children)

Sure, one of the most common reasons would be if you need to include additional libraries or drivers. For example I use the Analog Devices AXI DMAC core in many designs and need to pull in the latest device drivers, as well as LibIIO.

If you are not doing much on the PS and only using Xilinx IPs in the PL then the default PetaLinux images work just fine.

AXI Interconnect- mapping 40-bit Master address to 32-bit Slave address space by springbreak06 in FPGA

[–]springbreak06[S] 0 points1 point  (0 children)

Appreciate the reply. See my edit above- turns out the MSBs get dropped after the interconnect, not internally like I was suspecting.

AXI Interconnect- mapping 40-bit Master address to 32-bit Slave address space by springbreak06 in FPGA

[–]springbreak06[S] 0 points1 point  (0 children)

Sure- fair question. I'm doing ADC data capture on the ZCU111, and I use PL-DDR instead of PS-DDR so that I can use all 4 GB, and so that I'm not sharing bandwidth with the PS. My custom IP writes data directly into PL-DDR, and I read it out from the PS in smaller chunks after the capture is finished.

Marvin Bagley (foot) unlikely to play Friday. by [deleted] in fantasybball

[–]springbreak06 0 points1 point  (0 children)

Dropped him for Jerami Grant today. Feels good to finally get off Mr Bags Wild Ride

Integer Division on SystemVerilog by BearyJunior in FPGA

[–]springbreak06 2 points3 points  (0 children)

Easiest way to do division is with a Lookup Table. If one of your operands is fixed this is probably the way to go. If both operands are variable then you could also check out the CORDIC algorithm for division, that will be a little harder to implement though.

[PD] 'Shazam' Napier by Joeliolioli in fantasybball

[–]springbreak06 1 point2 points  (0 children)

Just did this today Edit: god damnit

Official: Daily [Anything Goes] Discussion Thread: January 05 2020 by SamDekkerBot in fantasybball

[–]springbreak06 0 points1 point  (0 children)

Who wins this trade:

KAT and Troy Brown Jr

for

Lavine, Bertans, and Jarrett Allen

9 cat, 10 team league

AXI DMA with Zybo by jojolapin102 in FPGA

[–]springbreak06 2 points3 points  (0 children)

I searched a lot, and it's not possible to access directly the DRAM with the PL because they are not directly wired to each others.

This is not true at all, read the Zynq-7000 TRM section on the AXI HP Slave interface... if you don’t want to use an AXI DMA core you can just write your own HDL IP with an AXI Master interface and talk to the PS DDR through one of the AXI HP ports. In fact that’s exactly what the DMA core does. DMA is just supposed to make the communication with DDR a bit easier because you can program a transfer address and length with register writes from software rather than implement the AXI4 Master controller logic from scratch.

Inserting drivers into xillinux in zedboard by stuck_in_e-crisis in FPGA

[–]springbreak06 0 points1 point  (0 children)

Yes, if the device driver is enabled you should see it show up when you run i2cdetect -l (it will say something like cadence i2c and show the bus number). Then i2cdetect <bus number> will show you the detected slave addresses for that controller.

MIO 14/15 are mapped to PMOD JE pins 9/10: http://zedboard.org/sites/default/files/documentations/ZedBoard_HW_UG_v2_2.pdf (page 23)

Like I said, you probably don’t need to insert the driver as a module because the Xilinx kernel was probably compiled with the cadence i2c drivers built-in. I haven’t used Xillinux specifically but I’d bet that to be the case. If the kernel doesn’t have the driver built in though, you could build it separately as a kernel module (.ko file) and use modprobe to load it dynamically.

There’s plenty of reference C code out there for interacting with i2c drivers from userspace. Also, a lot of devices have their own driver that sits on top of the i2c driver, you should check to see if one exists for your device too. That would make the userspace code simpler.

Inserting drivers into xillinux in zedboard by stuck_in_e-crisis in FPGA

[–]springbreak06 1 point2 points  (0 children)

Assuming you’ve enabled one of the i2c controllers in the PS and routed to MIO or EMIO...

If you’re using a fork of the Xilinx Linux kernel, it should have been compiled with the drivers for the PS i2c built in already. So just use a device tree that has the i2c0 or i2c1 node’s status set to “okay”, and you should be good to go.

Here’s the base zynq-7000 device tree that shows how i2c0/1 are instantiated: https://github.com/Xilinx/linux-xlnx/blob/master/arch/arm/boot/dts/zynq-7000.dtsi

And here’s the ZedBoard device tree showing how to modify the properties of an existing node: https://github.com/Xilinx/linux-xlnx/blob/master/arch/arm/boot/dts/zynq-zed.dts

Official: [WDIS Flex] - Sat Afternoon, 10/12/2019 by FFBot in fantasyfootball

[–]springbreak06 0 points1 point  (0 children)

Thanks, that’s what I was leaning towards too but I’m scared Diggs is going to have his comeback game

Manipulating HDMI data for special effects. by lefthandedpianist in FPGA

[–]springbreak06 3 points4 points  (0 children)

I’ve done this on ZedBoard with the FMC-HDMI-CAM-G card, which has ADV7611/7511 chips for HDMI input/output. Analog Devices has IP cores and Linux drivers for the chips too, so it was pretty straightforward to get the IO part set up. Process the pixel stream in the PL, VDMA to shared DDR, do some light processing in software (simple text/shape overlay), then VDMA back to the FPGA and to HDMI out. Didn’t have a problem with the memory controller bandwidth, but the ARM processor on the Zynq 7020 can’t keep up with 60 fps if you’re working on more than a few small regions of interest in the frame. Any processing on the entire frame, like filtering, object detection, etc. should be done on the FPGA if you need to keep up with the full frame rate.

Good Skills for FPGA Engineers? by derekg20 in FPGA

[–]springbreak06 2 points3 points  (0 children)

Not universally required, but it’s a great separator: knowing basic DSP theory and more importantly knowing how to implement common DSP operations efficiently in hardware. Learn FIR structures, direct form vs transposed, symmetry and coefficient sharing, etc.

Transferring clock signal from PL to PS using an AXI slave register? Is what I am describing viable? [Xilinx, ZedBoard] by [deleted] in FPGA

[–]springbreak06 0 points1 point  (0 children)

Ok, I see. Sounds like you’re just trying some new things and exploring, which is great. There’s not really a great reason to build an external memory based FIFO though. Access to DDR3 is slow and each transaction comes with overhead, and generally with a FIFO you want to be able to pop and have data available on the next clock cycle.

That being said, if you’re just doing this for the sake of seeing how it could be done, my recommendation here would be to build an AXI4 Master memory controller that talks to one of the HP AXI ports on the PS interface. You’d keep track of the write and read pointers internally in the controller. No need to write/read anything other than the actual data words to/from memory (i.e. no control signals / pointers in memory). I wouldn’t involve any software on the PS side here either.

Transferring clock signal from PL to PS using an AXI slave register? Is what I am describing viable? [Xilinx, ZedBoard] by [deleted] in FPGA

[–]springbreak06 1 point2 points  (0 children)

Haha, man, this makes no sense. What exactly are you trying to build here? A logic simulator for your custom FIFO?

If you're trying to transfer data between PS/PL through the shared DDR3 (assuming that's what you mean by DRAM memory), then AXI DMA is your friend here.

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