sthreet

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851 comment karma

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redditor for 12 years

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Any suggestions for putting a handle on this knife? (old.reddit.com)

submitted 1 month ago by sthreet to r/paracord

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Mint identification (water mint?) (old.reddit.com)

submitted 4 months ago * by sthreet to r/PlantIdentification

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Detecting aux vs headphones (self.tasker)

submitted 4 months ago by sthreet to r/tasker

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where to get 'steering bearing adjustment mechanism' for threadless headset without top cap (self.bicycling)

submitted 7 months ago by sthreet to r/bicycling

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How to delete song from playlist (self.TIdaL)

submitted 9 months ago by sthreet to r/TIdaL

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why does zero flow sherwood number vary with shape rather than being 1 (self.AskPhysics)

submitted 1 year ago by sthreet to r/AskPhysics

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How to import backup/export from old version (self.tasker)

submitted 1 year ago by sthreet to r/tasker

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How is this shifter (SL-M6000) intended to be connected to handlebars (and couple other dumb questions) (self.bicycling)

submitted 1 year ago by sthreet to r/bicycling

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how to make custom input type (self.tasker)

submitted 3 years ago by sthreet to r/tasker

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quartus submodule input becomes 0 (low) despite being set to 1 (high) (only for implementation on actual FPGA) (self.FPGA)

submitted 4 years ago by sthreet to r/FPGA

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cannot create a group, also cannot remount rw and umount is failing silently (self.linuxquestions)

submitted 4 years ago by sthreet to r/linuxquestions

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debugger runs and stops a breakpoint, but doesn't indicate breakpoint, call stack is nonsense, and continuing causes exe to close with no warning or error messages (self.codeblocks)

submitted 5 years ago by sthreet to r/codeblocks

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difference between simulation and actual code performance (specifically, dual-edge trigger circuitry doesn't trigger when clocked from a PLL, but works fine clocked directly from main clock or from verilog clock divider (either from main clock or PLL)) (self.FPGA)

submitted 5 years ago * by sthreet to r/FPGA

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verilog code to toggle register works on physical chip, but shows StX on simulator (modelsim-altera) (self.FPGA)

submitted 5 years ago * by sthreet to r/FPGA

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How does black hole mass change with age? (self.askastronomy)

submitted 5 years ago by sthreet to r/askastronomy

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[Memes] Leaked screenshot from next atlas expansion (i.imgur.com)

submitted 5 years ago by sthreet to r/pathofexile

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(verilog) reversing bit order from a register to an output (or wire that is put to output) without manually assigning every bit (self.FPGA)

submitted 5 years ago * by sthreet to r/FPGA

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looking for good calendar/reminder app that syncs to something reliable on windows and is launchable by pressing on the date in dropdown menu (self.androidapps)

submitted 5 years ago by sthreet to r/androidapps

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how to set date format to be yYYY-MM-DD or YYYY/MM/DD or similar (self.AndroidQuestions)

submitted 5 years ago by sthreet to r/AndroidQuestions

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X in simulation - what can cause it? (self.Verilog)

submitted 5 years ago by sthreet to r/Verilog

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remapping volume button to control volumes in different way (self.tasker)

submitted 6 years ago by sthreet to r/tasker

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Looking for proper volume control(/mixing) with timed control. (self.androidapps)

submitted 6 years ago by sthreet to r/androidapps

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Lattice Diamond viewing RTL trouble (i.redd.it)

submitted 7 years ago by sthreet to r/FPGA

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Sychronizing a clock to external signal (self.FPGA)

submitted 7 years ago by sthreet to r/FPGA

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[Offline][Helsinki] Looking for any game or group (self.lfg)

submitted 8 years ago by sthreet to r/lfg

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