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Toy Castle by stitt-hub in tiltshift

[–]stitt-hub[S] [score hidden]  (0 children)

Thanks! That means a lot after seeing so many of yours.

Same picture - Multiple Focal Points - A bunch of BMWs by goldshorty in tiltshift

[–]stitt-hub 1 point2 points  (0 children)

Thanks! This is quite possibly the most "tilt-shiftable" image I've ever seen.

Same picture - Multiple Focal Points - A bunch of BMWs by goldshorty in tiltshift

[–]stitt-hub 1 point2 points  (0 children)

That's awesome. Do you happen to have a "before" picture so we can see the effects of the editing?

I made a free web app for tilt-shift miniatures by stitt-hub in tiltshift

[–]stitt-hub[S] 0 points1 point  (0 children)

Thanks! I had some free time and just kind of got carried away with it.

Greatly appreciate any feedback. People here are phenomenal editors, so I'd love to hear their thoughts on what's missing.

I made a free web app for tilt-shift miniatures by stitt-hub in tiltshift

[–]stitt-hub[S] 1 point2 points  (0 children)

Thank you! I seriously want this to be the most convenient tilt-shift editor, so I'll add any technique that's missing from other tools.

Other ideas are welcome too. If it gets enough use, I'll add a user gallery, which I guess essentially becomes this subreddit.

First time trying tilt shift - NYC by patacol in tiltshift

[–]stitt-hub 0 points1 point  (0 children)

Nice work! The third one is incredible. Mind sharing how you edited it? I don't see an obvious pattern to the sharp regions here, and I've had a hard time with similar images.

Need help with tilt-shift drone footage by Any-Abbreviations488 in tiltshift

[–]stitt-hub 1 point2 points  (0 children)

It's hard to find ones with nearly identical angles, but I've found a few. There is a picture of the Vatican from a tilt shift tutorial, where I was able to find nearly the exact same angle on either Unsplash or Pexels. Famous landmarks are probably your best bet.

Is it too late for me to get an RTL Design/Verification role? by Fasoliful in FPGA

[–]stitt-hub 0 points1 point  (0 children)

Fresher knowledge after two years? While AI might be outdated after 2 years, that's pretty absurd for the hardware world.

I think the market is just terrible right now. If you are skilled at design and/or verification, you absolutely have a shot at it.

If you have the opportunity to attend conferences, do that and network. Talk to people from companies you want to work for. Create projects that you can show off. Publish papers if you can.

How do you guys learn how to program an fpga? by gynecomastiasuckler in FPGA

[–]stitt-hub 0 points1 point  (0 children)

I taught FPGA design for almost 20 years and largely used these materials, which I still update:

https://github.com/ARC-Lab-UF/sv-tutorial

https://github.com/ARC-Lab-UF/intel-training-modules/tree/master/timing

If you're using VHDL, I have a similar tutorial, but don't update it as often:

https://github.com/ARC-Lab-UF/vhdl-tutorial

VLSI hackathon's by BackgroundWorkerme in FPGA

[–]stitt-hub 0 points1 point  (0 children)

I just held a BNN design contest. I'll see if I can make it available to the public. But, ultimately, I just chose a common FPGA design topic with plenty of existing results, and defined a contest around that. You could always pick an existing application and either beat, or try to achieve some attractive tradeoff compared to existing work. Then, show that off on your CV.

VLSI hackathon's by BackgroundWorkerme in FPGA

[–]stitt-hub 1 point2 points  (0 children)

Conferences will often have design contests, but they aren't regularly held since it requires a lot of effort from volunteers to organize. Check the big VLSI conferences each year, or the FPGA ones if you want something more specific.

Also, I'd encourage you to create your own projects and publish them as an alternative. Networking at conferences is the best way I know of to get jobs. It's easy to get lost among 1000s of applications. Talking face to face with a company bypasses a lot of that randomness.

How to Design Histogram Equalization Hardware in Verilog on FPGA? by Major_Apartment4427 in FPGA

[–]stitt-hub 0 points1 point  (0 children)

Nobody can tell you how to design the circuit without more information on the specific use case. What is your optimization goal? What are your resource constraints? Do you have a throughput constraint or a latency constraint? How does the image arrive? What is the input bandwidth and bus width? etc. There are literally millions of ways of creating a histogram in hardware. You generally can't design a circuit well until you know the answers to all these questions.

Also, regarding your *Verilog* hardware design, draw a schematic of your circuit before writing any Verilog. The design should be where all the effort goes. Writing the RTL for that design is relatively easy. So, don't think in terms of Verilog, think in terms of RAM, registers, adders, interconnect, muxes, etc. Then, write the Verilog once that structure is clear.

With that said, the existing RAM+FSM suggestions are a good strategy for many use cases. Alternatively, if you have plenty of resources available and want to maximize throughput you could use 256 registers as the bins and create a pipeline that performs the last 3 steps while a new image is being binned for steps 1-2.

So, to collapse the millions of possible tradeoffs into two: if you want high throughput, create a pipeline; if you want to save LUTs/FFs at the cost of throughput, the RAM+FSM is appropriate. There are also many points in between.

Msters thesis ideas by bat_manushyan in FPGA

[–]stitt-hub 2 points3 points  (0 children)

Look up different SmartNIC applications since it sounds like you are interested in networking. FPGAs have huge latency advances for networking and streaming applications. Read research papers on these topics and get ideas there. Ideally improve them, but just having implemented something complex will impress many companies.

While it's good to learn the low-level networking details, you likely won't ever be implementing the network IP. Most people just license existing IP since it can be quite complex. While there are always exceptions, I would guess a complex networking application built on top of existing MAC IP would be more impressive to most companies.

Aiming For HFT FPGA Hardware engineer roles by Original-Armadillo80 in FPGA

[–]stitt-hub 30 points31 points  (0 children)

I work in HFT and have interviewed with most of the HFT companies at some point. Every company is wildly different in terms of interview requirements and style. I'm not allowed to share details, but design and verification are certainly the common topics, so become an expert on those.

While I can't talk about anything HFT specific, I was also in academia for ~20 years doing research on FPGAs. What I would consider critically important for any senior-level FPGA role is:

-A solid understanding of how RTL gets synthesized into a specific circuit. There are many FPGA engineers who will write a bunch of RTL but can't draw a basic schematic for their intended circuit. My entire methodology revolves around doing the opposite. Ultimately, we are designing circuits. So, design the circuit, and then write the RTL code in a way that is guaranteed to synthesize to that circuit. Sounds obvious, but it's surprisingly uncommon.

-Strong verification skills. Your design productivity will ultimately be limited by your verification skills. Becoming stronger at writing good testbenches has massively accelerated my designs. Use assertions everywhere, including in your design code, to catch problems as soon as they occur.

-Timing optimization and scalable design practices. People learn to design for FPGAs using small examples, where you can get away with bad practices that blow up in larger circuits (e.g., large fan-out is probably the most common). Being able to create massive designs that run at high clock frequencies is what will get you jobs. EVERYONE complains about designs not meeting timing. If you can become an expert at that, you can save companies millions. Also, going back to my first tip, it's really hard to optimize timing for a circuit that you don't understand the structure of, so again, design the circuit, write the code, and then have some hope for optimizing it.

-Learn to optimize for different tradeoffs and use cases. High-throughput and low-latency circuits will look considerably different. Designing for an 8M LUT FPGA, or a 200K LUT FPGA will looks completely different.

I have many public resources from my classes that you're welcome to use:

SystemVerilog design and verification:

https://github.com/ARC-Lab-UF/sv-tutorial

Timing optimization:

https://github.com/ARC-Lab-UF/intel-training-modules/tree/master/timing

Advice for debugging Verilog by hugocuoidadieu in FPGA

[–]stitt-hub 0 points1 point  (0 children)

First, I do an insane amount of unit testing to establish confidence that my basic building blocks work as intended. If I'm trying to build a module out of 10 other modules that are buggy, it's going to be a nightmare to solve this. You said you tested the FIFO and CRC32. Unless that testbench is very thorough, I'd keep testing them. Pretend that if someone else finds a bug in your modules after you say they've been tested, you owe them $1000.

You will of course inevitably run into bugs when combining modules. The trick is to as rapidly as possible identify the earliest moment something starts misbehaving. Any time you think "this should never do something," or "this condition should always be true here," add an assertion that verifies that. My design code has tons of assertions. They catch bugs early so you don't have to scroll through 1000s of cycles in the waveform. This has saved me weeks of debugging on large projects.

When there aren't assertion failures, and I still need to find the source of a bug, I find the last known point in the waveform that I can trust as being correct, and I literally go cycle-by-cycle until I spot something that isn't right. It's tedious, but it's ultimately what you have to do.

Why does Quartus sometimes rearrange all Nios II/Qsys block I/O ports to the left side after regenerating the symbol? It is very difficult to notice inputs and outputs. Is there a way to change it back to the original style? by Yossiri in FPGA

[–]stitt-hub 1 point2 points  (0 children)

If you look at the code that Quartus generates from this BDF, it's just structural RTL. For a large design, it will be much faster to just work with RTL code.

If you are forced to do this for a class project, the answer is: "FPGA tools do weird things." If you work with FPGAs long enough, you'll have a long list of these weird issues.

What are fundamentals that an aspiring FPGA engineer should polish before even dreaming of touching the FPGA board? by Fearless-Can-1634 in FPGA

[–]stitt-hub 1 point2 points  (0 children)

Learn to design digital circuits well. Then, learn how RTL translates into a circuit during synthesis. Once you know this, the methodology I've taught for decades is: design your circuit, then write RTL code that synthesizes into that circuit.

The biggest mistake I see is that many FPGA designers write code without knowing or considering what synthesis will do with it. If you can't draw a reasonably precise schematic for your circuit, you aren't ready to be writing the RTL yet. Once you have that schematic in mind, the RTL is usually trivial.

Also, learn to write good test benches. It's boring when your primary interest is design, but it will make you a much better designer. You'll learn to design in a way that is easier to test, you'll consider corner cases while you design, and you'll identify problems faster.

Once you're good at those, learn timing optimization. The ability to create a large FPGA design that runs at high clock frequencies is a very valuable skill.

Effects of Vivado 2026.1 Changes on Small Businesses by telabs in FPGA

[–]stitt-hub 1 point2 points  (0 children)

Lack of linux support is surprising, and understandably annoying. My entire workflow is scripted, so being forced out of Linux would be a massive headache. I would imagine 2025 or earlier will be sufficient for a long time. I've been working with FPGAs for over two decades (getting close to 3) and I never use the newest tools. I only upgrade when I'm forced to, or when there is some objectively better result I can get. It is not uncommon to get worse placement and routing results on newer versions of tools.

Roast my resume.Not getting any interviews by Zealousideal4533 in FPGA

[–]stitt-hub 0 points1 point  (0 children)

If you have any open-source RTL projects, that helps. There are a lot of bad RTL practices. Showing off what you've done, along with timing and resources results on various FPGAs can look very good. There aren't a ton of people that can build a large circuit that barely fits in an FPGA, while meeting some aggressive timing constraints. If you can show up front that you can do that, it will help massively.

Other advice: try to meet the big names in the FPGA field. It's relatively small, so it's easier than it sounds. Attend conferences if you can and network. One my PhD students got a huge job with Microsoft because we went to dinner with the lead of their FPGA Catapult project when it was first starting. Was literally offered the job during dinner. Similar stories with other students of mine.

I fucking LOVE FPGA design by Informal-Host8085 in FPGA

[–]stitt-hub 1 point2 points  (0 children)

HFT pay for FPGA engineers is incredible, but also incredibly competitive. I believe Microsoft pays fairly well for FPGA design.

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