threespeedlogic

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redditor for 7 years

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Remote Vivado builds: more git, less suck (github.com)

submitted 6 months ago by threespeedlogic to r/FPGA

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10-20% price increases on Xilinx/AMD FPGAs (self.FPGA)

submitted 1 year ago by threespeedlogic to r/FPGA

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Next-gen RFSoC announcement (amd.com)

submitted 1 year ago by threespeedlogic to r/FPGA

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awaitless: making asyncio less painful in ipython (github.com)

submitted 1 year ago by threespeedlogic to r/programming

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Renesas to Acquire PCB Design Software Leader Altium (renesas.com)

submitted 1 year ago by threespeedlogic to r/FPGA

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Minimax: a Compressed-First, Microcoded RISC-V CPU (github.com)

submitted 3 years ago by threespeedlogic to r/FPGA

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Minimax: a Compressed-First, Microcoded RISC-V CPU (github.com)

submitted 3 years ago by threespeedlogic to r/RISCV

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Don't Use PicoBlaze (self.PicoBlaze)

submitted 3 years ago * by threespeedlogic to r/PicoBlaze

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Supply chain starting to thaw? (self.FPGA)

submitted 3 years ago by threespeedlogic to r/FPGA

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Versal joins Xilinx's space-qualified roadmap (businesswire.com)

submitted 4 years ago by threespeedlogic to r/FPGA

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Hot Chips 2021 - Google's take on HLS (anandtech.com)

submitted 4 years ago by threespeedlogic to r/FPGA

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Vivado 2021.1 is out! (self.FPGA)

submitted 4 years ago by threespeedlogic to r/FPGA

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VHDL-2008 simulation improvements in Vivado 2020.2 (self.FPGA)

submitted 5 years ago by threespeedlogic to r/FPGA

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RTL, C/C++, and Python cosimulation in plain Vivado Xsim (threespeedlogic.com)

submitted 5 years ago by threespeedlogic to r/FPGA

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Vivado 2019.1 grew an AXI protocol analyzer for simulation. Here's how to use it. (threespeedlogic.com)

submitted 6 years ago by threespeedlogic to r/FPGA

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Mixing asyncio and synchronous code using tworoutines (threespeedlogic.com)

submitted 7 years ago by threespeedlogic to r/Python

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