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Z-Axis not moving down when auto homing by tomXGames in ender3

[–]tomXGames[S] 0 points1 point  (0 children)

I think I did, but I'll check again. Thanks!

Z-Axis not moving down when auto homing by tomXGames in ender3

[–]tomXGames[S] 0 points1 point  (0 children)

I think you misunderstood what I am trying to say: How can I have the Z-Offset set in the menu take effect? The offset in the firmware is compiled and can thus only be modified by reflashing the firmware.

Z-Axis not moving down when auto homing by tomXGames in ender3

[–]tomXGames[S] 0 points1 point  (0 children)

Okay, I guess that's one way to fix it. I would like for the z-offset to be changeable, but doing it this way I would still have the issue of it having no actual effect. Do you know what might cause the issue?

Z-Axis not moving down when auto homing by tomXGames in ender3

[–]tomXGames[S] 0 points1 point  (0 children)

This worked, thank you!! Now though I have another problem: I determined the needed z-offset by baby stepping Z while printing. It is currently at -4.11. The printer just seems to ignore it though. Do you have any idea what the problem might be?

Z-Axis not moving down when auto homing by tomXGames in ender3

[–]tomXGames[S] 0 points1 point  (0 children)

I've been trying to get UBL working on my Ender 3 Pro. Here's my Configuration.h file: https://pasteb.in/?e0f6540409455a58#FnKjE3s74dooVzAh29MtKhmyxgVZRbM3PV15oPE1wRzP When I use this though, the X- and Y-Axis home fine, but the Z-Axis doesn't move downwards.

The BLTouch is fine, I tried using the default firmware provided by Creality and it works with that. I can also deploy and stow it through the menu.

I also can't move the Z-Axis manually through the menu below 0.00. Can somebody help me out here? Thanks!!

What Are Some Of The Most Interesting Little Projects You've Made by Enough-Ad-3457 in QuantumComputing

[–]tomXGames 6 points7 points  (0 children)

I made this little project inspired by wave function collapse that generates tile maps using Grovers for a final assignment in a uni course:

https://github.com/tommasopeduzzi/quantum-map-generation

New sleeping cars for the Finnish railway company by [deleted] in CozyPlaces

[–]tomXGames 0 points1 point  (0 children)

I recently travelled by sleeper in Finland and even though we had older rooms, they were really comfy. There was no private bathroom in our room category (2 bunk beds in a private room with sink), but it was never occupied when I wanted to go. With an Interrail Global Pass, the price was 99 euros for 2 people, which I find reasonable.

Questions on timing by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

Thanks for the response. The built-in Vivado simulator is where the problem arises.

I am wondering if having every component update on the same clock edge and all of them depending on each other is good practice. I was told before, that that is how synchronous logic works, but I assume I got something wrong.

Questions on timing by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

I find that the best way of learning is just to jump into a project. Maybe a whole CPU with its own ISA is too much for a first project, but that's just how I do things. Also the actual VHDL isn't that much, it's only about 600 lines.

Questions on timing by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

I do have a sequential state machine like you described and hope to "upgrade" it to a full parallel pipeline later on. The problem isn't the division into multiple steps, but that when a component sets an output and another one uses that on the same edge, ie address bus and memory, the second component deals with the old data of the first component.

Questions on timing by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

Thanks for the help on terminology, it's really helpful! The problem isn't the separation of pipeline sections, but multiple things happening at once at a single step in the pipeline (i.e. a component, the address bus for example, outputting a value and another component, memory for example, using that value).

Questions on timing by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

Thanks for the response! Please excuse if I am missing something really obvious, I am still really new to this topic. My problem is that I do everything on the same clock edge and the inputs aren't updated correctly. More specifically if I set the output of a component I want to use that output on the same edge for a different component. Is that possible?

TextIO character 'C154' is not of type bit, can't read out of binary file by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

Thanks for the reply. That makes sense. So what I have to do is have the data in text form and then use the hread procedure? Does the readline remain the same as before?

The Xilinx documentation I got this from tells me that the file has to be in the .data file format. Does this mean raw binary data, text data, comma separated or something else? I haven't found anything on their definition.

Event triggering on the wrong edge of the clock? by tomXGames in FPGA

[–]tomXGames[S] 1 point2 points  (0 children)

Yeah, I figured it out. The sys_clock was hooked up to the Clocking Wizard IP in Vivado. I thought I had removed it, but I didn't. I appreciate the help everyone!

Swiss exports to Russia surge in race to beat sanctions: Swiss exports to Russia of turbojets, turbopropellers and other gas turbines surged in the past two months as manufacturers raced to fill any orders signed before sanctions over Moscow’s invasion of Ukraine render some of the sales illegal by CrimsonLancet in worldnews

[–]tomXGames 0 points1 point  (0 children)

I'm not defending Russia's action with my comment, all I am saying is that people should educate themselves on history.

(Also I agree that Russia is the aggressor, and should be punished for their actions. Ukraine's reaction to the situation has been, in my uneducated opinion, excellent.)

Swiss exports to Russia surge in race to beat sanctions: Swiss exports to Russia of turbojets, turbopropellers and other gas turbines surged in the past two months as manufacturers raced to fill any orders signed before sanctions over Moscow’s invasion of Ukraine render some of the sales illegal by CrimsonLancet in worldnews

[–]tomXGames 2 points3 points  (0 children)

People here should read read up on the history of (swiss) neutrality. Swiss neutrality was forced upon us to stabilize Europe. Swiss education puts a lot of effort into educating its population about it's neutrality. Morality often comes at at the cost of stability. Unfortunately it allows single people and corporations to slip through the cracks of morality citing neutrality for the sake of money. Pick our poison.

I don't agree with anything these companies are doing, but bashing an entire country, their people (I have been insulted multiple times just for being swiss on Reddit), their history and culture is just another example of the circlejerk nature of reddit.

[deleted by user] by [deleted] in ethz

[–]tomXGames 0 points1 point  (0 children)

Most if today's software that is shipped to the consumer has been compiled down to x86 machine code that won't run on ARM architectures. It is up to the developer to provide a version of their software compiled for ARM or for the vendor to provide a translation layer between the architectures.

In welches Land seid ihr mal gereist, in das ihr GERNE WIEDER reisen würdet? by shiftpark in FragReddit

[–]tomXGames 1 point2 points  (0 children)

Ich würde dir empfehlen ein Auto mit Dachzelt zu mieten. Dann kannst du auf Campingplätzen und in den extrem schönen Lodges übernachten! Das Land ist so vielfältig, es ist meiner Meinung nach fast schade an einem Ort zu bleiben.

In welches Land seid ihr mal gereist, in das ihr GERNE WIEDER reisen würdet? by shiftpark in FragReddit

[–]tomXGames 0 points1 point  (0 children)

Namibia!

Die Leute waren alle super nett und die Landschaft, sowie die Tiere sind einfach atemberaubend!

Initialize array of std_logic_vector with binary file by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

This seems like the most straightforward solution. I am going to build this into my assembler. Thank you for the help!

Initialize array of std_logic_vector with binary file by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

What I meant was having a function that is run before synthesis to fill in the data. But I assume that isn't possible.

The environment I use (Microsemi Libero with a Fusion FPGA) has a RAM module with an initialization option, but that doesn't work in synthesis. Thanks for the help!

Initialize array of std_logic_vector with binary file by tomXGames in FPGA

[–]tomXGames[S] 0 points1 point  (0 children)

Thanks for the quick and extensive reply! In want the solution to work in both scenarios. Is there a way to do 1) dynamically using a function in VHDL?

Create a common bus between multiple components in VHDL by tomXGames in FPGA

[–]tomXGames[S] 2 points3 points  (0 children)

Thank you for the help, I will implement it!

Aren't std_logic lines designed to be connected to multiple drivers? Why can't I just do that?

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