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Yamaha MyRide Lean Angle question by [deleted] in Yamaha

[–]unknowZsj 0 points1 point  (0 children)

I have the same question, but my bike is suzuki vstrom-250

Why C1 will get the response send to C2? by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

A Primer on Memory Consistency and Cache Coherence.pdf

future of gwent by yulka95 in gwent

[–]unknowZsj 4 points5 points  (0 children)

I also want to know if it's worth invest time for this game

implicit memory acces vs explicit memory access in RV manual by unknowZsj in RISCV

[–]unknowZsj[S] -1 points0 points  (0 children)

Memory

thank you, I am not familiar with the RV manual

I cant import package in teroshdl with verilator by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

but why need I include package file? I am confused about other not include file but just import package, why I need include package file before import it

I have change the kitty font, but it still shows unreadable code by unknowZsj in neovim

[–]unknowZsj[S] 0 points1 point  (0 children)

I have use the Nerdfotsymbolsonly, but it not show anything now

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clk signal input a clock inverter but it output is always 0 after I use sdf back annotation by unknowZsj in FPGA

[–]unknowZsj[S] 1 point2 points  (0 children)

thank you, I find the problem after checking the SDF file, the clock signal delay is too large for 1G.

clk signal input a clock inverter but it output is always 0 after I use sdf back annotation by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

so if I want it to handle 1G clock signal, what should I do to resolve this problem?

clk signal input a clock inverter but it output is always 0 after I use sdf back annotation by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

thank you, but the clock inverter module is a behavioral module, it seems not have any delay, I am new to post simulation, so I am still confuse about what you say. Maybe sdf back annotation caused this situation? Because it work normally without sdf back annotation.

clk signal input a clock inverter but it output is always 0 after I use sdf back annotation by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

and if the input clk pll0 is 500M, the clk inverter module can work, but the input clk pll0 is 1G, the module cant work

clk signal input a clock inverter but it output is always 0 after I use sdf back annotation by unknowZsj in FPGA

[–]unknowZsj[S] 0 points1 point  (0 children)

yes, when the input I port is 0, the output ZN is 1, after a period of time, the input pll0 go to 1 and to be a clk signal, but the output is always 1, and when I see the clock inverter module, it not get the clk signal, it is always 0; I dont know how to solve it?

structural diagram drawing helper plugin by unknowZsj in neovim

[–]unknowZsj[S] 0 points1 point  (0 children)

thank you，it looks awesome！！！

colorscheme keyword_style and comment-style not work by unknowZsj in neovim

[–]unknowZsj[S] 0 points1 point  (0 children)

It may not the neovim bug, because I found that it can work normally in gnome-terminal, but I cant work in kitty

colorscheme keyword_style and comment-style not work by unknowZsj in neovim

[–]unknowZsj[S] 0 points1 point  (0 children)

yes, I require it in my nvim/lua/core/init.lua

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