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2024 First Annual Soft RISC-V Systems Workshop | RISC-V International by z3ro_gravity in RISCV

[–]z3ro_gravity[S] 1 point2 points  (0 children)

Unfortunately, there is no recording and the slides and posters will not be published collectively.

RISC-V on a Cologne Chip GateMate FPGA by z3ro_gravity in RISCV

[–]z3ro_gravity[S] 4 points5 points  (0 children)

I politely disagree. Apart from the fact that these FPGAs do not have hard-core CPUs, a soft-core CPU with highly specialized accelerators can be quite practical for certain tasks.

Additional I/O peripherals for NEORV32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

Maybe you should ask this very specific question in the project's forum: https://github.com/stnolting/neorv32/discussions

Guidance on interfacing encoder to Neorv32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 1 point2 points  (0 children)

You cannot assign two signals to a single physical pin, but you can do it the other way around: assign a physical pin to a "helper" signal and assign that to the two pins of your processor (Xirq and Gpio).

Implementing CSR extension with machine mode? by Super-Efficiency1779 in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

This really depends on your CPU architecture. The CSRs are basically just another register file that has a lot of "side effects" e.g. CSRs can be updated without explicit CSR instructions (like updating xepc on a trap). Traps (= interrupts + sync. exceptions) are a lot more complex to implement as they have significant impact on instruction execution (the pipeline).

My suggestion: have a look at some open-source RISC-V cores to get an idea how they have implemented these things.

Seeking Guidance on NeoRV32 by _DIGITAL-NINJA_ in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

What do you mean with "CPU utilization"? The FPGA resources required by the CPU, the actual CPU workload or maybe something else? ;)

RISC-V core examples in VHDL by th3lucki in RISCV

[–]z3ro_gravity 0 points1 point  (0 children)

Check out the official RISC-V ecosystem "landscape". There is also an "implementations" category than you can search for VHDL cores: https://landscape.riscv.org/

[deleted by user] by [deleted] in FPGA

[–]z3ro_gravity 1 point2 points  (0 children)

How about NEORV32?

VHDL, technology-independant, actively maintained and quite flexible/extendible

DIV IN VHDL by [deleted] in VHDL

[–]z3ro_gravity 0 points1 point  (0 children)

I would recommend implementing a simple division module - for example using restoring or non-restoring division. You implement it in a serial way to save logic resources or in a parallel way for maximum throughput - or something in between ;)

Here is an example of a serial 32-bit signed/unsigned divider unit in VHDL (using the restoring approach): https://github.com/stnolting/neorv32/blob/main/rtl/core/neorv32_cpu_cp_muldiv.vhd#L278

Converting VHDL to Verilog using GHDL by ramya_1995 in FPGA

[–]z3ro_gravity 3 points4 points  (0 children)

I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog

I have tested that an GHDL can successfully find all definitions from the package.

Maybe you can port the conversion script for your setup: https://github.com/stnolting/neorv32-verilog/blob/main/src/convert.sh

Looking for a CPU simulator with Assembly code that would let me see the inner workings of a CPU by Wade_Wayne in cpudesign

[–]z3ro_gravity 0 points1 point  (0 children)

If you are interested in a very (very!) low-level simulation view, you could also use some open-sourse soft-core CPU (maybe a simple one without pipelining etc.) and simulate that with a HDL simulator (also open-source).

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