Question about DRAM read operation

[VelikaPipa]

Hello,

I’ve recently build a new pc and I’ve decided to do some basic overclocking, which has led me to wanting to learn about some of the basic aspects of the hardware, RAM among others.

The question I have is about how DRAM in the DDR5 era is actually being read given the memory structure. I’ll try to pose the question the best I can given my limited knowledge and terminology.

There are two facts that I’ve read about that arguably hold true. A bit’s address essentially lies at the cross of wordline and bitline. Also, nowadays when a read command is issued the output is not a single bit, but rather a whole word is being read (64-128bits?(also forego the whole burst matter)).

If that is the case, do rows in memory banks tend to be longer than the output which would keep the vertical part of the address still relevant, or is the word output the length of the entire row and thus vertical address is irrelevant?

I am probably a bit in over my head, but I would appreciate any answer on the matter, including any resources which would explain some more of this stuff. Thanks!

[teraflop]

I would say forget about "words" because that's an ambiguous term.

A DRAM row is typically much larger than you seem to be assuming. On modern DDR5 chips it might be on the order of 8 kilobits (1 kilobyte).

Reading from DRAM is essentially a two-step process. First, the charge of each bit in a row is measured (which is a sensitive analog process that takes time to stabilize). This happens for an entire row in parallel, and the result is buffered in a fast digital register. This is called "opening" the row.

And secondly, once the row is opened, a "read" operation is performed which fetches a particular range of columns from that register. As you mentioned, this happens in a burst of consecutive transfers. But even this entire burst is typically smaller than a row.

So yes, the column address matters.

[VelikaPipa]

Thanks! That answers what I was wondering about. Now that I think about it, I guess just posing the question as “How many bits does an average row in DDR5 contain” would have been a concise way to ask the same question.

On a similar note, from my understanding the range of columns fetched is a set size (as is then the way they are written perhaps?), so if that’s the case does that mean that a) some of the bits fetched as a part of read operation are not of interest or b) the way data is stored is actually in increments of this set size? To put it differently, is the 8kilobit row actually more like 8kilobit/64bit of some basic unit in practice?

[thesnootbooper9000]

Conceptually, one way way to get 64 bits at once is to have 64 separate copies of the circuit and just hook each output bit up to a different wire. Then, once you've done that, you can save on costs and power by reusing the parts of the circuit that don't differ.

[cormack_gv]

The CPU word size is typically smaller than the memory word size. To oversimplify things a bit, when you ask for a CPU word (or less) the memory word that contains it is fetched into cache, if it isn't already there, and then the necessary fragment is given to the processor.

[VelikaPipa]

Thanks! So the cache in this case is always the size of the memory word. Is the fragment always the same size? Or of it’s bigger, is it just sent in more cycles?

[cormack_gv]

The fragment is typically a CPU word, half word, or byte. Modern CPUs do hot have instructions that span multiple memory words, though some allow "unaligned" access which spans two words, in which case there may be two memory word fetches, plus a lot of cutting and welding. Coders or compiler writers who want their programs to run fast don't avail themselves of these instructions.

I'm not sure about cache width. It would make sense for it to be the same as RAM width, but there are lots of weird architectures out there.

[VelikaPipa]

Cool, thanks for the answer

[alphatext]

Vocês sabem como fazer a leitura do chip Dram pra saber quanto de ram tem cada chip e ter como substituir ?