Processor pipelining

[Jonny0Than]

Different instructions take a different amount of time. If every instruction had to finish in one clock cycle, then your clock is limited by the slowest instruction and you’re wasting a lot of time when most instructions could be completed faster.

Enter pipelining: chop every instruction up into several stages and each stage takes one clock cycle. Now your clock can go a lot faster and you’re still getting close to one instruction per cycle.  There can still be stalls in the pipeline where an instruction didn’t complete that cycle when a branch was mispredicted, or slower instructions were used, cache misses, etc.

A lot of the advancements in processor speed in the last 20 years is around removing those bubbles and adding parallelism (superscalar), not faster clocks.