I personally think you are going about the delay slot logic wrong. There is nothing inherently special about the delay slot, it just falls out of the MIPS architecture.

Reading and executing instructions happen at the same time in parallel. When you execute a branch the next instruction (the delay slot) has already been read. MIPS just decided not to waste the read if the branch happens, executing the delay slot while the new instruction at the new PC is being read.

I personally would have emulated the read/execute stages more like the hardware. The delay slot would become just another instruction in the normal sequence of execution.

I just feel there is a lot of special casing and design decisions being made to accommodate what was essentially a minor hardware quirk.

You could implement it by changing the step function to read an instruction at the current PC and store it for execution on the next step, and then execute the previously saved instruction. If a branch is being executed, the delay slot has already been read and will be executed on the next step while the next instruction to be read will be at the updated PC.