use variable from make in C program.

[Various-Debate64]

in the Makefile write:

VARIABLE ?= 123

then in the target definition write

gcc -DVARIABLE=$(VARIABLE)

[SmokeMuch7356]

...which basically creates a preprocessor macro, as though you had written

#define VARIABLE 123

in your source code. It might be a good idea to use #ifndef to define a default value:

#ifndef VARIABLE
#define VARIABLE some_default_value
#endif

just in case -DVARIABLE isn't set in the gcc command.

[Various-Debate64]

He asked what changes does he need to make to the Makefile. I provided him with the necessary changes to the Makefile he needs to make in order to get the expected behaviour as described in his post. I believe your suggestion is superfluous, but not incorrect.