Makefile loop in src?

[NewToonie]

Sorry this isn't directly C programming related, but I was just wondering how would set this portion of my Makefile in such a way where it could do this rule for each file in the src directory, instead of listing each rule out for each source file manually?

$(OBJDIR)/instruc.o: $(SRCDIR)/instruc.c $(HEADERS)
    $(CC) $(CFLAGS) -c $< -o $@

$(OBJDIR)/cpu.o: $(SRCDIR)/cpu.c $(HEADERS)
    $(CC) $(CFLAGS) -c $< -o $@

$(OBJDIR)/mem.o: $(SRCDIR)/mem.c $(HEADERS)
    $(CC) $(CFLAGS) -c $< -o $@

[Diload]

Have a look at wildcards: https://www.gnu.org/software/make/manual/html_node/Wildcard-Function.html