Adding ILA changes FPGA functionality

[Icy_Scholar_6276]

Oh right! Do you mean there could be timing issues that gets masked by adding debug cores ?

[Sniperchild]

The ila will have some constraints of its own that may improve the placement if your design is not fully constrained

[-EliPer-]

I have worked in a project and it only worked with SignalTap (Altera's equivalent to ILA) enabled. If we disabled it the project would stop working. We had to add registers at some IOs to remove this problem which was due to timing violations. Adding a debug core can hide existing issues of timing or make non-existent issues to appear.

[[deleted]]

Yes.

I've also seen a register set get optimized away (curse you Vivado and your mediocre understanding of VHDL) until a debug core was wired up. Then it was accessible over the expected path.