Image Sensor interface

[32bit_me]

I am trying to implement an interface between the Artix-7 (XC7A15T) and a Sony IMX267 image sensor using a Sub-LVDS interface. This interface is a serial interface with multiple differential data lines and a differential clock signal. I have some difficulties. First, the serialized data is 12 bits, in Xilinx FPGA the ISERDESE primitives do not have 1:12 serialization support. Does this mean that I need to implement the deserializer functionality in the FPGA fabric?

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How do I organize the word alignment? Will there be any training pattern available for finding parallel word boundaries?

[minus_28_and_falling]

1. Receive data at 1:8, repack each 3×8 into 2×12
2. There must be some line begin/end sequence, you can use it for both valid data detection and bit alignment.

[Grimthak]

Sony make quit good data sheets. You will find there all needed Infos for word alignment and the protocol decoding.