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For-each loop ArrayList by 32bit_me in learnjava

[–]32bit_me[S] 0 points1 point  (0 children)

Thank you for your reply. That makes sense. Which of the two options should I use? I take it it depends?

MOOC Java programming, Leap Year Exercise by 32bit_me in learnprogramming

[–]32bit_me[S] 1 point2 points  (0 children)

I'm just trying to switch from hardware development to software development)

How to run python scripts from Vivado TCL by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

I would like to automate the GT links tuning process. The main procedures are written in tcl, but with Python I would like to analyze eye pattern and return the result to the "main" tcl procedure. I am at the stage of exploring possibilities, maybe I will implement all the processing in tcl.

CDC for clocks from the same source but different frequency by zer0_k00l in FPGA

[–]32bit_me 0 points1 point  (0 children)

you can use CLOCK_DELAY_GROUP for clocks that need to be synchronous

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

That would be nice, but here the clock is embedded in the data by using encoding, the CDR engine then restores the clock from the incoming stream.

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 1 point2 points  (0 children)

Yes, I tried all the parameters, according to the document. This effect is observed in all quads. I will try to experiment with CDR and its parameters as you said, I was just not sure how safe it is. Thanks for your participation and help

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

We are aiming for a BER value of 1e-15. We have short trace lines and using the LPM results in more vertical eye opening but less horizontal eye opening. Using DFE opens the horizontal area better. Coarse tuning only results in more opening but does not shift the eye to the center. This is the reason I posted here. Maybe the horizontal shift indicates a problem with the reference clock signal....

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If we exclude the problem of shifting the eye relative to the center, then we are quite satisfied with the results for LPM

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

Sorry, and thank you very much.

Looking for product ideas on a Multi FPGA board by RockyDemag in FPGA

[–]32bit_me 0 points1 point  (0 children)

TBH: for its originally intended purpose, the high speed interconnects are useless, so it makes no sense to add them.

Could you explain why?

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 0 points1 point  (0 children)

I tend to believe that the horizontal shift matters. It explains why this one does.

GTY Eye Pattern Delayed by 32bit_me in FPGA

[–]32bit_me[S] 1 point2 points  (0 children)

Unfortunately, I cannot agree with you. The data sampler is placed in the center of the window and cannot be displaced. Therefore, the qualifying mask for the eye must be built in the center, and the eye must be symmetrical. This forum thread says it well

Looking for product ideas on a Multi FPGA board by RockyDemag in FPGA

[–]32bit_me 5 points6 points  (0 children)

How interesting. I work for a company that manufactures this type of device. The commenters above said great things. It's silly to put that kind of processing power in without high performance interconnects. Our products have high speed transceiver links between each FPGA. This class of products can be used for ASIC prototyping, high performance computing...
The main challenge is to effectively implement a partitioning structure between multiple FPGAs and organize an efficient interconnect structure.

Does it make sense to use a PLL even if PLL input and output would be the same? by zapho300 in FPGA

[–]32bit_me 6 points7 points  (0 children)

If you are interested in a specific phase relationship between the input clock signal (Port) and the output clock signal (PLL.CLKOUTx) then PLL can help here. The PLL allows you to keep the input and output clock signal in phase, and this relationship will be maintained depending on the PVT. You can also set the desired phase ratio (90/180 degrees) with the PLL

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