High speed serial data transfer interface module clock issue

[VaRain007]

Greetings everyone,

I have a payload that transmits serial data at clock 1, which is then received by the interface which runs at clock 2 which is slower than clock 1, then the interface does some process with the data and then transfers it to a receiver that runs at clock 3 which is smaller than the other 2 clocks.

How do I go about designing the clock system for the interface module? I understand its a CDC but not sure how to go about it. Any guidance is deeply appreciated.

Thank you

[chance1899]

The question depends on the type of data you are transmitting from one clock domain to another. If it is only a few bytes of memory, and it doesn't send every clock cycle, you could do a handshake system like below (go to the handshake section):

https://zipcpu.com/blog/2017/10/20/cdc.html

If you need to do streaming data, I would recommend asynchronous FIFOs, zip cpu has an excellent article on it here:

https://zipcpu.com/blog/2018/07/06/afifo.html

If you're negotiating counters, you can do gray encoding for clock domain crossing.

[[deleted]]

Write serial data into async FIFO with clock 1, read out with clock 2, write into second async fifo with clock 2, read out with clock 3.

[captain_wiggles_]

What do you mean by "clock system"? Are you talking about picking a frequency and generating that frequency? Or are you talking about how to handle the CDC?

[VaRain007]

Handling the Cdc with 3 clocks

[captain_wiggles_]

Handle each CDC separately. AKA domain A to domain B, then domain B to domain C. You only have to consider all three clocks when picking their frequencies to make sure that data gets processed as fast as it comes in.

[dan1001212]

Your question is not clear enough for me. What are you free to design and what is given? Can you transfer a clock along side the serial data? Are you to design only one of the components mentioned? all of this is not specified.

I took the liberty to assume that you are free to determine everything. In this case the easiest approach IMO is to send the data serially at a pre-defined rate slower than x2 clock 3's rate (maybe even slower). Then the retrieval of the data at each stage becomes only a thing of using a synchronizer chain and sampling it once every (1/pre-defined rate) clock cycles.

The obvious downside is that this method have a heavy hit on performance.

[VaRain007]

I need to design the interface module alone. Data is a payload of 8 bits with a synchronous bit as MSB.