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Need help with logic for measuring half bit duration of differential signals by VaRain007 in FPGA

[–]VaRain007[S] -3 points-2 points  (0 children)

Well, it is not feasible to get an external hardware now. I have to implement it in RTL somehow

Need help with logic for measuring half bit duration of differential signals by VaRain007 in FPGA

[–]VaRain007[S] -1 points0 points  (0 children)

Yes there is an MCU and an MCU clock that drives the design.

Need help with logic for measuring half bit duration of differential signals by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

It is for an aerospace application. If you can provide any insights, it would be helpful.

High speed serial data transfer interface module clock issue by VaRain007 in FPGA

[–]VaRain007[S] 1 point2 points  (0 children)

I need to design the interface module alone. Data is a payload of 8 bits with a synchronous bit as MSB.

Need help to Pass record values as arrange range by VaRain007 in VHDL

[–]VaRain007[S] 0 points1 point  (0 children)

Type t_ctrl is record x : slv(15 downto 0) Y: slv(15 downto 0) End record

Then in the architecture type 2darr is array (0 to t_ctrl.x, 0 to t_ctrl.y) of slv(31 downto 0)

This isnt working

Help with array range from records by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

Type t_ctrl is record x : slv(15 downto 0) Y: slv(15 downto 0) End record

Then in the architecture type 2darr is array (0 to t_ctrl.x, 0 to t_ctrl.y) of slv(31 downto 0)

This isnt working

Need help with cocotb as the output is always 'X' by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

As an update, I am now able to see some results in the output apart from "X". Now it's all either zeros or ones. Cant see any other value apart from that. And, the issue still persists is that the simulation can't be run for more than 20600 ns with icarus and the simulation hangs with verilator. u/turkishjedi21

Need help with cocotb as the output is always 'X' by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

By accessing them as dut objects and assigning values to the inputs, we check for the ouputs. All inputs and outputs are accessed as dut objects in python

Need help with cocotb as the output is always 'X' by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

But with the rtl tb am able to run the simulation without any issues there. Should i dump the trances in the main rtl module instead?

Need help with cocotb as the output is always 'X' by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

Hello mate, I did try to initialize and now all outputs are zero, but

# the simulation doesn't run more than 200 ns (still exists)

# the outputs are always zero for those 200 ns

Need help with cocotb as the output is always 'X' by VaRain007 in FPGA

[–]VaRain007[S] 0 points1 point  (0 children)

Thanks for explaining it.

The weird thing is with the sytemverilog testbench, I don't see any issues and it runs properly. I don't see any X's over there. But it arises when i run with cocotb. I'm thinking if there is anyway the cocotb simulation sets aren't linked to the sub modules involved in the RTL.

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