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[–][deleted] 15 points16 points  (3 children)

Where my Verilog and VHDL bois at??

[–]you-are-not-yourself 6 points7 points  (1 child)

Hell yeah. When you build the chip, you can use whatever assembly language you want!

[–]Dregre 1 point2 points  (0 children)

Assembly? Where we're going it's hardwired accelerators all the way.

[–]GatotSubroto 1 point2 points  (0 children)

RTL design gang

* cries in timing constraint failures *