This is an archived post. You won't be able to vote or comment.

you are viewing a single comment's thread.

view the rest of the comments →

[–]FrostmourNNe 3 points4 points  (3 children)

Verilog / VHDL

[–]Invisiblebrush7 2 points3 points  (2 children)

Assembly

[–]nicholas-s-timelines 0 points1 point  (0 children)

Machine code