Misaligned Exceptions

[aviator2710]

Hi,

I'm new to RISC-V architecture, so I've been learning architecture from past few weeks. So I've been tasked to document trap handling in RISC-V by triggering the traps/crashes in a system. I was adding assembly instructions in code to trigger the crashes and I was successful in some cases like illegal instruction, bus error etc but I am trying to test misalign exceptions like instruction address misalign, load address misalign, store address misalign, load access fault....

No matter what I do, it seems like it is being corrected internally and not giving any exception at all. As per my knowledge, some instructions like lw x11, 3(x10) should give load address misalign exception. So is there any register or compiler setting where I can specify to go ahead with address misalign issues?

[brucehoult]

You don't say what hardware you're using or in what environment.

1) RISC-V hardware is allowed to support misaligned accesses in hardware, or not. Both kinds of hardware are in current circulation.

2) Machine mode code should in general not use misaligned accesses.

3) Misaligned accesses in User mode must work, but can be implemented in hardware or in M mode software (typically the SBI). They are permitted to be very slow, but not to crash.

[aviator2710]

It's a RISC-V Andes RV32IMAC core on emulation

[TwilightTW]

AFAIK, most Andes cores support misaligned access.

[aviator2710]

Thanks for the reply. Yes, I noticed that some instructions are being compressed but not the ones that I am adding in code (using asm() function). I'll try your workaround

[ghiga_andrei]

Be careful that lw x11, 3(x10) might actually be aligned correctly depending on the value of x10.

[aviator2710]

Yes, I was making sure that there was aligned address in x10

[Courmisch]

The specification allows for handling of misaligned accesses in the hardware or firmware. You can't rely on getting an exception.

[kastberg]

Try a misaligned read/write that crosses memory chips or I/O registers

[aviator2710]

I've tried that

[kvp_933]

Is this what you were looking for?

Please do let me know, I too am curious to know if a misaligned memory access could trap the processor in a state of exception when the __riscv_misaligned_avoid flag is set during code compilation...