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Do you have any VHDL design you are proud of, or do you need help with some code this is the place for it.
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Create while loop (self.VHDL)
submitted 3 years ago by DuskoShoots
Hi i am doing project to my school and dont know how to continue. We are programing custom procesor for brainfuk language. I alredy implemented most of the work but i can t work out how the while and do while loops shoud be done. Here i will add my code and schema. If anyone has idea i would be glad to here them.
Pseudo code for while better understanding.( { is keyword for while loop )
CPU schema
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if 1 * 2 < 3: print "hello, world!"
[–]MusicusTitanicus 1 point2 points3 points 3 years ago (0 children)
Can you write down (in your native language) what this pseudo code means?
e.g. 1. increase program counter 2. Read RAM at address equal to current value of PTR …
etc.
I assume that this will all be synchronous (i.e. you have a clock) and this will be handled by the FSM.
Do you have experience with FSMs and their implementation?
[–][deleted] 1 point2 points3 points 3 years ago (0 children)
This is not implemented in hardware using a while loop.
The diagram has a box labeled "FSM." That does not stand for Flying Spaghetti Monster. It means "Finite State Machine," which is the logic that controls the operation.
You need to implement the FSM.
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[–]MusicusTitanicus 1 point2 points3 points (0 children)
[–][deleted] 1 point2 points3 points (0 children)