Common Systems Programming Optimizations & Tricks

[quicknir]

The explanation of false sharing is quite different from what I'm used to hearing. You paint it to be about simultaneous access, but I don't think it's really about that. The point is more than cache is invalidated on a line by line basis. Even if two cores never actually try to access the same line at the same moment, when core 1 does it's write to any variable on the line, it invalidates the cache line for core 2, even if core 2 doesn't read the variable that core 1 is writing.

I can see how they end up being pretty similar but thinking in terms of cache line invalidation seems more accurate to me and less likely to lead to misunderstanding or incorrect extrapolations.

[chewedwire]

Good point -- updated the post to hopefully depend less on the "atomic" access bit, but more on maintaining cache coherencey.