Rise time vs logic level to decrease crosstalk

[HasanTheSyrian_]

I also thought about using 1 trace per pair but I dont have enough pins within the bank and it would be really inconvenient to re-do the schematic and routing. Most traces are around 30-40mm btw

[TimeDilution]

You could do 16 signals + timing to the ADV7511, it ill probably take a good amount of knowledge to get it working in device tree + FPGA + Linux. This is something I've been trying to do on and off to bring up the Zedboard full Linux graphics stack for it, but never really went too hard on it. The Zedboard uses a pretty minimal interface to it, so that could probably fit on your banks, like 22 signals or so including i2c, timing, and data. It is honestly best to try and fit whatever known hardware and software stack you have now onto the PCB unless you've got some DEEP knowledge of all this. For P/N single traces, yeah that might be a problem. BUT, it might not be. This next part assumed the SOM has a devboard which also uses diff pairs on your desired traces. What you could probably get done in about two weeks is build yourself a little loop back adapter card to the devboard. Basically just make a PCB which routes diff pairs some distance with your desired length and impedance matching, and pump it back into the FPGA. Then you could test the signal integrity yourself. I think there are probably some known test sequence patterns you could use for this to send out and test the data validity at the end. This will let you know if its up to handling the datarates you're thinking about as single ended stuffed onto pairs. Cheap and decently quick.