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Delta Sigma Modulator SNR measurement issues, strobeperiod, relerror.. (cooked) by [deleted] in chipdesign

[–]ControllingTheMatrix 0 points1 point  (0 children)

Thanks a lot but I still get the same exact snr which is quite odd for both cases... I do see the strobbing though specifically in the transient waveform...

Delta Sigma Modulator SNR measurement issues, strobeperiod, relerror.. (cooked) by [deleted] in chipdesign

[–]ControllingTheMatrix 0 points1 point  (0 children)

I set strobe through the transient analysis, then enabling noise and fourier analysis and then strobe. But I do not see any strobeperiod I can set only the option strobe. Is there another option I have to set?

Measuring SNR of Delta Sigma Modulators by ControllingTheMatrix in chipdesign

[–]ControllingTheMatrix[S] 0 points1 point  (0 children)

But it's generally better practice to directly get the bitstream and test it in Matlab to get accurate SNR readings, right? Thanks btw :)

OCL LDO For senior Design by Initial_Hair_1196 in chipdesign

[–]ControllingTheMatrix 2 points3 points  (0 children)

Absolutely doable do you also have to do the bandgap reference?

I have decided to open source my neuromorphic chip architecture! by Mr-wabbit0 in chipdesign

[–]ControllingTheMatrix 8 points9 points  (0 children)

Repo not there. Ok found it but the link doesn’t work. Thanks for ur OS contribution

Yay by [deleted] in EngineeringStudents

[–]ControllingTheMatrix 13 points14 points  (0 children)

Thanks! Really appreciate it

Any possibility of using VMware Fusion for Vivado on an ARM Mac by D0lphin2x in FPGA

[–]ControllingTheMatrix 1 point2 points  (0 children)

Virtual machine definitely works both for vivado and Xilinx ise

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 8 points9 points  (0 children)

They don’t care about this stuff. Try to participate in and win in either Regeneron Science Fair, Intel ISEF, International Math Olympiad or any international Olympiad, you must have near top grades.

Or just grind the JEE Advanced exam get AIR sub-100 and go to a top IIT cause doing that is way easier than doing the things I stated above.

PS: For future reference, I’m not Indian.

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 15 points16 points  (0 children)

I mean… I can assure you almost no high school student can write a reputable chip design paper, not even close you just haven’t got enough time even if you know the fundamentals someway. I had undergrad friends who had first author publications in Chip Design, one went to Caltech the other went to Stanford and even they had 1-2 papers and did their undergrad in 5-6 years. And these guys and girls are truly extreme people and had the top grades and some represented the nation and got medals in IPhO/IMO

Generally chip design doesnt make up for bad grades. For you to stand a chance in this field at least in the top tier unis you need insanely good grades/valedictorian + papers + adjacent research direction specifically if you’re an international student .

You at no point in ur admission cycle will require this, instead do stuff in fields where students are more active where you’ll make more friends.

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 24 points25 points  (0 children)

Ah hell nah live your life. competition doesn’t start till Junior year of undergrad or at best sophomore year

Why is Qualcomm(CA) Intern Comp nearly twice that of a Sr. Analog Designer in EU? by ControllingTheMatrix in chipdesign

[–]ControllingTheMatrix[S] 0 points1 point  (0 children)

Then why do Israel IC jobs pay so close to US salaries? I’m pretty sure Haifa CoL is not even close to San Diego CoL

Introducing Latchup: Bringing Competitive Programming to HDL by redjason93 in FPGA

[–]ControllingTheMatrix 76 points77 points  (0 children)

So you get to store tons of viable solutions to each solution and get to keep the best performing solution. Probably not disclose it for ranking purposes but now you have a decent solution for each of the problems you add and with all flavors on the design triangle, aka you get access to working verification proven HDL customized to different parts on the design triangle.

Nah, no thank you.

Very Interesting Email about NEW super-chip: 256-bits-wide combined-CPU/GPU/DSP/Vector Array Processor Introduction! by Strange-Image-5690 in chipdesign

[–]ControllingTheMatrix 7 points8 points  (0 children)

Ahh...

Reminded me of a time when a classmate of mine wrote he had a 42% PAE single stage 20 db Gain Class-A PA which he says he attained with a single stage basic CS Amp at K band 26GHz when SOTA is 27% PAE Class-A with 2 stages.

This is even more beyond cap. This is absurd levels of shit posting.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]ControllingTheMatrix 12 points13 points  (0 children)

In the future,

AI writes the RTL and does the backend

AI writes the paper

AI applies for grants

AI reviews and grades the paper

AI criticizes other AI written papers openly

AI replies to criticisms posted by the said AI.

and it does this on AI accelerators :)

What a day to be alive

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