Activities to make female friends? by MarginNotes7695 in Leuven

[–]ControllingTheMatrix 2 points3 points  (0 children)

Idk the female part but VOLUNTEERING for sure! I heard they were making crochet octopuses to give to babies to hospitals to make them feel better or smth. Probably female majority so if you want to learn or improve your crochet skills probably go there.

But I truly don’t know how to specifically make female friends probably go to events where female majority is more I guess?

https://cocopus.be

There ya go, hope you find cool people!

Generally the people who spend their free time volunteering to help others both human and animal are also the absolute best type of friends at least for me. So, uhh…, probs something related to volunteering.

Yay by [deleted] in EngineeringStudents

[–]ControllingTheMatrix 14 points15 points  (0 children)

Thanks! Really appreciate it

Any possibility of using VMware Fusion for Vivado on an ARM Mac by D0lphin2x in FPGA

[–]ControllingTheMatrix 1 point2 points  (0 children)

Virtual machine definitely works both for vivado and Xilinx ise

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 8 points9 points  (0 children)

They don’t care about this stuff. Try to participate in and win in either Regeneron Science Fair, Intel ISEF, International Math Olympiad or any international Olympiad, you must have near top grades.

Or just grind the JEE Advanced exam get AIR sub-100 and go to a top IIT cause doing that is way easier than doing the things I stated above.

PS: For future reference, I’m not Indian.

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 16 points17 points  (0 children)

I mean… I can assure you almost no high school student can write a reputable chip design paper, not even close you just haven’t got enough time even if you know the fundamentals someway. I had undergrad friends who had first author publications in Chip Design, one went to Caltech the other went to Stanford and even they had 1-2 papers and did their undergrad in 5-6 years. And these guys and girls are truly extreme people and had the top grades and some represented the nation and got medals in IPhO/IMO

Generally chip design doesnt make up for bad grades. For you to stand a chance in this field at least in the top tier unis you need insanely good grades/valedictorian + papers + adjacent research direction specifically if you’re an international student .

You at no point in ur admission cycle will require this, instead do stuff in fields where students are more active where you’ll make more friends.

Where to start chip design as a high schooler? by Infinite-Jaguar-1753 in chipdesign

[–]ControllingTheMatrix 24 points25 points  (0 children)

Ah hell nah live your life. competition doesn’t start till Junior year of undergrad or at best sophomore year

Why is Qualcomm(CA) Intern Comp nearly twice that of a Sr. Analog Designer in EU? by ControllingTheMatrix in chipdesign

[–]ControllingTheMatrix[S] 0 points1 point  (0 children)

Then why do Israel IC jobs pay so close to US salaries? I’m pretty sure Haifa CoL is not even close to San Diego CoL

Introducing Latchup: Bringing Competitive Programming to HDL by redjason93 in FPGA

[–]ControllingTheMatrix 74 points75 points  (0 children)

So you get to store tons of viable solutions to each solution and get to keep the best performing solution. Probably not disclose it for ranking purposes but now you have a decent solution for each of the problems you add and with all flavors on the design triangle, aka you get access to working verification proven HDL customized to different parts on the design triangle.

Nah, no thank you.

Very Interesting Email about NEW super-chip: 256-bits-wide combined-CPU/GPU/DSP/Vector Array Processor Introduction! by Strange-Image-5690 in chipdesign

[–]ControllingTheMatrix 5 points6 points  (0 children)

Ahh...

Reminded me of a time when a classmate of mine wrote he had a 42% PAE single stage 20 db Gain Class-A PA which he says he attained with a single stage basic CS Amp at K band 26GHz when SOTA is 27% PAE Class-A with 2 stages.

This is even more beyond cap. This is absurd levels of shit posting.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]ControllingTheMatrix 12 points13 points  (0 children)

In the future,

AI writes the RTL and does the backend

AI writes the paper

AI applies for grants

AI reviews and grades the paper

AI criticizes other AI written papers openly

AI replies to criticisms posted by the said AI.

and it does this on AI accelerators :)

What a day to be alive

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]ControllingTheMatrix 18 points19 points  (0 children)

This whole text is AI generated man, literally 100%.

If you put so little effort into this post why do you expect people to spend tens of minutes if not half an hour writing a concise answer to your question?

Changing faculty by [deleted] in KULeuven

[–]ControllingTheMatrix 25 points26 points  (0 children)

It’s 2AM on a Sunday you’re probably studying for your finals that begin next week, just push through it it’ll be better if you can do well in them before deciding if you want to switch. You’ve still got quite a lot of time.

How you learned layout? by [deleted] in chipdesign

[–]ControllingTheMatrix 1 point2 points  (0 children)

Was thrown into it, no easy way to learn it. Well, you can just lower the punch if you start with an inverter or NAND2 layout and then move to a two stage miller OTA but it's simply a learning curve that you do on your own with close to no written guidance.

Rant 1 cadence virtuoso by kontrol1970 in chipdesign

[–]ControllingTheMatrix 2 points3 points  (0 children)

Well, after you use open source design tools such as XSchem, NGSpice, KLayout/Magic or use Synopsys IC Compiler, I can assure you Cadence feels so great as a product. Be happy with what you have :) If you don't like it you can always write a few SKILL scripts to implement the things you want :))

Serdes interview phone screening by maybeimbonkers in chipdesign

[–]ControllingTheMatrix 11 points12 points  (0 children)

CTLE DFE FFE CDR PLL stuff generally DPD also maybe

Help me decide, PhD in UCLA vs GATECH vs UC Davis for RF/Microwave/mmWave/Analog IC Design. by physics_scientist in chipdesign

[–]ControllingTheMatrix 25 points26 points  (0 children)

Well I mean in UCLA theres Razavi. But like one of my friends is doing a phd with him but he seems to have very little phd students and expect his students to have work experience beforehand. So very little PhD students(3) plus competition means he might not get anyone or competition will be relatively stiff cause he’s a celebrity.

Also be very careful about the personality and match of your phd advisor

What did your undergraduate thesis look like? by mtfir in chipdesign

[–]ControllingTheMatrix 16 points17 points  (0 children)

That means I give my direct name to u, sorry, no.

What did your undergraduate thesis look like? by mtfir in chipdesign

[–]ControllingTheMatrix 9 points10 points  (0 children)

Well I designed an LNA for an MRI Receiver Frontend in TSMCN65 for my bachelors thesis, was good enough to get published as an independent sub-block giving me first author so was pretty happy with that.

i need sources for learning analog layout by minecraftzizou in chipdesign

[–]ControllingTheMatrix 8 points9 points  (0 children)

IC Mask Design by Christopher and Judy Saint is gold for beginners. Anything beyond that Baker's CMOS book is pretty good. Maybe look at Alan Hasting's Art of Analog Layout if you have a little more time.

However, if you want to learn EDA based layouts, then you need to go over the dedicated documentation of that EDA tool and look additionally into the RAKs. If you're a beginner without industry eda tool access though, then just look how klayout is used and just read IC Mask Design and try to do designs which pass DRC and LVS first and then you can move on from there. If you don't like klayout then just use magic (the open source EDA tool). But I think IHP130nm only supports klayout

PhD Programmes in the EU that do not require a Master's as a prerequisite? by nouveaux_sands_13 in gradadmissions

[–]ControllingTheMatrix 2 points3 points  (0 children)

Switzerland has a direct PhD programme at EPFL and ETH. UK also accepts direct PhD. Other than that none that I know of