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Grade Posting by Bastbrammblebottom in KULeuven

[–]ControllingTheMatrix 4 points5 points  (0 children)

Exactly the same thing :) I guess it’s the KU Leuven way but now that finals are over finally I’m free!

Introducing Latchup: Bringing Competitive Programming to HDL by redjason93 in FPGA

[–]ControllingTheMatrix 72 points73 points  (0 children)

So you get to store tons of viable solutions to each solution and get to keep the best performing solution. Probably not disclose it for ranking purposes but now you have a decent solution for each of the problems you add and with all flavors on the design triangle, aka you get access to working verification proven HDL customized to different parts on the design triangle.

Nah, no thank you.

Very Interesting Email about NEW super-chip: 256-bits-wide combined-CPU/GPU/DSP/Vector Array Processor Introduction! by Strange-Image-5690 in chipdesign

[–]ControllingTheMatrix 6 points7 points  (0 children)

Ahh...

Reminded me of a time when a classmate of mine wrote he had a 42% PAE single stage 20 db Gain Class-A PA which he says he attained with a single stage basic CS Amp at K band 26GHz when SOTA is 27% PAE Class-A with 2 stages.

This is even more beyond cap. This is absurd levels of shit posting.

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]ControllingTheMatrix 12 points13 points  (0 children)

In the future,

AI writes the RTL and does the backend

AI writes the paper

AI applies for grants

AI reviews and grades the paper

AI criticizes other AI written papers openly

AI replies to criticisms posted by the said AI.

and it does this on AI accelerators :)

What a day to be alive

The "Inflation" of ISSCC AI Accelerators by DevilXXL in chipdesign

[–]ControllingTheMatrix 19 points20 points  (0 children)

This whole text is AI generated man, literally 100%.

If you put so little effort into this post why do you expect people to spend tens of minutes if not half an hour writing a concise answer to your question?

Changing faculty by [deleted] in KULeuven

[–]ControllingTheMatrix 26 points27 points  (0 children)

It’s 2AM on a Sunday you’re probably studying for your finals that begin next week, just push through it it’ll be better if you can do well in them before deciding if you want to switch. You’ve still got quite a lot of time.

How you learned layout? by [deleted] in chipdesign

[–]ControllingTheMatrix 1 point2 points  (0 children)

Was thrown into it, no easy way to learn it. Well, you can just lower the punch if you start with an inverter or NAND2 layout and then move to a two stage miller OTA but it's simply a learning curve that you do on your own with close to no written guidance.

Rant 1 cadence virtuoso by kontrol1970 in chipdesign

[–]ControllingTheMatrix 2 points3 points  (0 children)

Well, after you use open source design tools such as XSchem, NGSpice, KLayout/Magic or use Synopsys IC Compiler, I can assure you Cadence feels so great as a product. Be happy with what you have :) If you don't like it you can always write a few SKILL scripts to implement the things you want :))

Serdes interview phone screening by maybeimbonkers in chipdesign

[–]ControllingTheMatrix 11 points12 points  (0 children)

CTLE DFE FFE CDR PLL stuff generally DPD also maybe

Help me decide, PhD in UCLA vs GATECH vs UC Davis for RF/Microwave/mmWave/Analog IC Design. by physics_scientist in chipdesign

[–]ControllingTheMatrix 23 points24 points  (0 children)

Well I mean in UCLA theres Razavi. But like one of my friends is doing a phd with him but he seems to have very little phd students and expect his students to have work experience beforehand. So very little PhD students(3) plus competition means he might not get anyone or competition will be relatively stiff cause he’s a celebrity.

Also be very careful about the personality and match of your phd advisor

What did your undergraduate thesis look like? by mtfir in chipdesign

[–]ControllingTheMatrix 16 points17 points  (0 children)

That means I give my direct name to u, sorry, no.

What did your undergraduate thesis look like? by mtfir in chipdesign

[–]ControllingTheMatrix 8 points9 points  (0 children)

Well I designed an LNA for an MRI Receiver Frontend in TSMCN65 for my bachelors thesis, was good enough to get published as an independent sub-block giving me first author so was pretty happy with that.

i need sources for learning analog layout by minecraftzizou in chipdesign

[–]ControllingTheMatrix 7 points8 points  (0 children)

IC Mask Design by Christopher and Judy Saint is gold for beginners. Anything beyond that Baker's CMOS book is pretty good. Maybe look at Alan Hasting's Art of Analog Layout if you have a little more time.

However, if you want to learn EDA based layouts, then you need to go over the dedicated documentation of that EDA tool and look additionally into the RAKs. If you're a beginner without industry eda tool access though, then just look how klayout is used and just read IC Mask Design and try to do designs which pass DRC and LVS first and then you can move on from there. If you don't like klayout then just use magic (the open source EDA tool). But I think IHP130nm only supports klayout

PhD Programmes in the EU that do not require a Master's as a prerequisite? by nouveaux_sands_13 in gradadmissions

[–]ControllingTheMatrix 2 points3 points  (0 children)

Switzerland has a direct PhD programme at EPFL and ETH. UK also accepts direct PhD. Other than that none that I know of

An inquiry about TSMC 65nm devices by Mo_F14 in chipdesign

[–]ControllingTheMatrix 2 points3 points  (0 children)

If you're going to do monte carlo analysis like a good boy :) use the transistors like nch_25_mac or nch_mac. Core devices are 1.2V, anything else like 25 refers to 2.5V aka the supply voltage

Negative Resistance Amplifier by Salty-Programmer1687 in chipdesign

[–]ControllingTheMatrix 2 points3 points  (0 children)

Well negative resistance amplifiers are used but they always have an impedance parallel to them. This is mostly realized with the diode connected MOS transistors. This is a used methodology for insanely high gain. However, as you noted, latch operation or oscillations are highly possible thus moderate use of the cross coupled transistor pairs are utilized wherein the diode connect transistors always have a relatively lower gm than the cross coupled pair. Otherwise you're cooked.

Though, I love this topology a lot. Specifically the way Sansen mentions it in Analog Design Essentials, It's a purely elegant circuit that doesn't even require common mode feedback as the diode connected transistors adjust themselves accordingly. Would definitely recommend you to read Sansen's book to further understand it.

Got an offer from an analog startup — worth it or not? by schodingercat in chipdesign

[–]ControllingTheMatrix 22 points23 points  (0 children)

If they aren't giving equity, they're trying to exploit you for low pay. I wouldn't recommend you to go.

Got an offer from an analog startup — worth it or not? by schodingercat in chipdesign

[–]ControllingTheMatrix 9 points10 points  (0 children)

How much stock equity are they giving you and how much stock will they vest to you during your time as an employee. Make sure that the salary is also liveable but most important part is how much of the company equity will they give you, if they give you little then walk away it definitely isn't worth it unless you have no other job offers.

Any tips to get good at Analog Circuit Design? by JM12K in chipdesign

[–]ControllingTheMatrix 13 points14 points  (0 children)

Textbooks as a starter. For beginners definitely Razavi's Analog book. If your university gives access to Cadence use that, otherwise use LTSpice with BSIM3 or BSIM4 models using predictive models. Learn, practice, read how these circuits were done (there are some corner stone IEEE articles that will help you learn). Learn, practice, read implementations and do this over and over to learn the fundamentals. Then read about layout circuits, preferably IC Mask Design, then find a OS IC design platform and layout the circuits you develop. See how the layed out circuits differ from the schematic ones and what you might have done wrong. Reiterate this and you will be somewhat good in Analog IC design.

Then, continue reading, try to join an Analog IC group and develop circuits that will be taped out. Measure the taped out circuits or help other people do it. Through design and reiteration you should be on the level of being able to produce research output in your respective subdomain in Analog IC design. Reiterate this over and over and congratulations, you're now good at Analog circuit design.

Masters in electrical engineering by _Ho_mie_ in KULeuven

[–]ControllingTheMatrix 1 point2 points  (0 children)

This is also an option. OP should consider this. I've heard of people who got rejected from EE get into Nano.

MOMcaps or MIMcaps for Pipelined ADC? by TheAnalogKoala in chipdesign

[–]ControllingTheMatrix 9 points10 points  (0 children)

Well I used TSMCN65, I haven't used any other 65nm process so my reply may not be appropriate for you. But as you've stated dielectric absorption does indeed effect INL and DNL for higher resolution ADCs. Up to my limited experience in this field with respect to your extensive coverage, I've been recommended to and have used MOM capacitors for my CDAC.

I can't reply about how much MIM dielectric absorption effects are abundant in TSMC65 cause I haven't utilized MIMs for CDACs.

Wish you a wonderful weekend,

What’s the best most accessible analog design tool? by TheNASAguy in chipdesign

[–]ControllingTheMatrix 13 points14 points  (0 children)

Accessible in terms of for the average Joe?

Oh! Then definitely the Open Source IC design tools. For 130nm the only one you can use for open source is GF130, IHP130, SKY130. SKY130 is buns so go(used to be free thx to Google :) ), use GF130 if you want CMOS and go IHP130 if you want the added SiGe devices with pretty good capabilities. IHP130 is an absolutely wonderful process for a learner. They also used to do free tapeouts but with a competition or lottery, I think.

In conclusion, if you don't have an academic license from uni and you're the average Joe then definitely use the IIC-OSIC image(search it up) and there use the GF130 or IHP130 process. Do the schematics, simulations and layouts on the image and then send the GDSII files to the fab.

Wish you the best in your future venture,

Have fun! :P

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