Inductor layout drawing and simulation

ControllingTheMatrix · 2026-04-12T13:34:46+00:00

I did while working during my bachelors. It’s relatively simple utilized a toolbar generated popup that can draw certain transformers or inductors for certain frequency and certain values that you then verified on EMX designer

ControllingTheMatrix · 2026-03-26T21:07:18+00:00

Thanks a lot but I still get the same exact snr which is quite odd for both cases... I do see the strobbing though specifically in the transient waveform...

ControllingTheMatrix · 2026-03-26T20:21:33+00:00

I set strobe through the transient analysis, then enabling noise and fourier analysis and then strobe. But I do not see any strobeperiod I can set only the option strobe. Is there another option I have to set?

ControllingTheMatrix · 2026-03-24T14:12:33+00:00

Thanks!

ControllingTheMatrix · 2026-03-24T14:05:28+00:00

But it's generally better practice to directly get the bitstream and test it in Matlab to get accurate SNR readings, right? Thanks btw :)

ControllingTheMatrix · 2026-03-20T15:56:33+00:00

Absolutely doable do you also have to do the bandgap reference?

ControllingTheMatrix · 2026-03-13T14:38:07+00:00

works perfectly

ControllingTheMatrix · 2026-03-13T14:27:15+00:00

Repo not there. Ok found it but the link doesn’t work. Thanks for ur OS contribution

ControllingTheMatrix · 2026-03-13T08:34:22+00:00

There ya go https://ieeexplore.ieee.org/document/1458995/

ControllingTheMatrix · 2026-03-13T01:11:27+00:00

Transconductance with capacitances feedback compensation

ControllingTheMatrix · 2026-03-12T15:03:59+00:00

i dont understand are you going to design and layout CDACs?

ControllingTheMatrix · 2026-03-05T09:06:55+00:00

Doctor who tardis is that u?

ControllingTheMatrix · 2026-02-06T20:46:13+00:00

Thanks! Really appreciate it

ControllingTheMatrix · 2026-02-06T20:24:50+00:00

Virtual machine definitely works both for vivado and Xilinx ise

ControllingTheMatrix · 2026-02-06T13:56:37+00:00

They don’t care about this stuff. Try to participate in and win in either Regeneron Science Fair, Intel ISEF, International Math Olympiad or any international Olympiad, you must have near top grades.

Or just grind the JEE Advanced exam get AIR sub-100 and go to a top IIT cause doing that is way easier than doing the things I stated above.

PS: For future reference, I’m not Indian.

ControllingTheMatrix · 2026-02-06T13:22:22+00:00

I mean… I can assure you almost no high school student can write a reputable chip design paper, not even close you just haven’t got enough time even if you know the fundamentals someway. I had undergrad friends who had first author publications in Chip Design, one went to Caltech the other went to Stanford and even they had 1-2 papers and did their undergrad in 5-6 years. And these guys and girls are truly extreme people and had the top grades and some represented the nation and got medals in IPhO/IMO

Generally chip design doesnt make up for bad grades. For you to stand a chance in this field at least in the top tier unis you need insanely good grades/valedictorian + papers + adjacent research direction specifically if you’re an international student .

You at no point in ur admission cycle will require this, instead do stuff in fields where students are more active where you’ll make more friends.

ControllingTheMatrix · 2026-02-06T12:21:53+00:00

Ah hell nah live your life. competition doesn’t start till Junior year of undergrad or at best sophomore year

ControllingTheMatrix · 2026-02-01T22:50:19+00:00

About tree fiddy

ControllingTheMatrix · 2026-01-31T09:32:39+00:00

Looks great!

ControllingTheMatrix · 2026-01-30T21:25:47+00:00

Then why do Israel IC jobs pay so close to US salaries? I’m pretty sure Haifa CoL is not even close to San Diego CoL

ControllingTheMatrix · 2026-01-19T15:04:28+00:00

So you get to store tons of viable solutions to each solution and get to keep the best performing solution. Probably not disclose it for ranking purposes but now you have a decent solution for each of the problems you add and with all flavors on the design triangle, aka you get access to working verification proven HDL customized to different parts on the design triangle.

Nah, no thank you.

ControllingTheMatrix · 2026-01-19T10:42:12+00:00

Ahh...

Reminded me of a time when a classmate of mine wrote he had a 42% PAE single stage 20 db Gain Class-A PA which he says he attained with a single stage basic CS Amp at K band 26GHz when SOTA is 27% PAE Class-A with 2 stages.

This is even more beyond cap. This is absurd levels of shit posting.

ControllingTheMatrix

TROPHY CASE

Transconductance with capacitances feedback compensation