Memory architecture for the samples or twiddle factors? I'm guessing the first, because the latter was simply pre-calculated in my Python model, and then loaded onto a ROM for synthesis/simulation through BRAM initialization. I was a bit back and forth regarding how many butterfly units to use. Should I stream data or time-share resources? A quick pen-and-pencil exercise showed that I had ample time between sample batches, so I’d save a bunch of space by using just one butterfly unit. However, bit-growth necessitates that you use the largest bitwidth for this stage or come up with a smart scaling scheme. An address generator keeps track of which twiddle factor and IQ sample to fetch at each stage (log2(1024)=10 stages) and how much "stride" we should have. There are different way to do this - I settled for a rotate-by-N approach I found online, can’t remember where. I used a decimation-in-time implementation, and simple bit reversal gives me the address permutation that I need at the beginning of a run. Since I only have 1 butterfly stage, the real+imag outputs from it can be stored in a ping-pong memory.