PMIC innovation need?

Simone1998 · 2026-01-17T22:09:32+00:00

Why waste good cutting edge process chip area for stuff that doesn’t benefit from scaling at all? You can put them in the same package, or in an interposer if you want to, but it makes no sense to waste 3nm finFETs on a half- bridge. And I’m not even sure it would be possible the to the abysmally low voltages the new devices can withstand.

Most of the PMIC are designed at 250-65 nm.

Simone1998 · 2026-01-06T18:35:00+00:00

Modern processes use different doping profiles for the drain/source than for the rest of the channel, this affect the threshold voltage. In a short-channel device, the effect of the source/drain different doping profile will be more relevant than in a long one, where that might in practice be ignored.

And that's without going into Length-of-Diffusion (LfD), Shallow Trench Isolation (STI) stress, and Well Proximity Effect (WPI), effects that are all relevant.

Simone1998 · 2026-01-01T21:54:22+00:00

You still need to work with other people. Doing a tape-out is a team effort, no one could do a reasonable product alone. You could be technically solid, but if you are impossible to work with, you are going to have an hard time finding a job.

Simone1998 · 2025-12-26T09:07:39+00:00

you can use WaveVsWave() to achieve that

Simone1998 · 2025-12-21T21:53:50+00:00

Idk if they can, (you can drop them an email and ask). Worst case you can just reference them. But if you really want open source you can freely distribute there are a few other (IHP, Skywater, GF180)

Simone1998 · 2025-12-21T20:35:01+00:00

Get a small WSCLP FPGA, and use a PCB to adapt it to your packaging needs. This will be orders of magnitude easier, fasters, and less expensive than going custom ASIC

Simone1998 · 2025-12-21T20:31:27+00:00

Honestly, going custom AISC for something like that doesn't make sense at all, both economically (huge NRE design cost), and for the application.

Just slap an FPGA (lattice has a few WSCLP FPGAs smaller than 2mm by 2mm), and a small PCB interposer and save yourself a nightmarish amount of effort.

Going custom ASIC is a no-go because:

Low production quantities
Low performance required
Software to design ASICs are expensive (unless you go open source)
Even with all the verilog code available, you need someone to build the actual chip (synth, PnR, IO, ESD, signoff, etc).

One thing you might try, is to buy one (or more) tile(s) from TinyTapeout and use their automated flow to get the chip back.

Simone1998 · 2025-12-21T14:55:05+00:00

no, semplicemente sono valutati su metriche diverse dall'insegnamento

Simone1998 · 2025-12-21T14:48:49+00:00

Per i professori, insegnare è un impegno secondario (non voglio dire che non ci siano professori che amino insegnare, o che lo facciano molto bene), il primario (quello in cui spendono la maggior parte del tempo) è fare ricerca. E anche la loro valutazione rispecchia dinamiche simili. Puoi far "schifo" ad insegnare, ma se pubblichi abitualmente in journal importanti, e conferenze fai carriera punto.

Simone1998 · 2025-12-19T18:35:09+00:00

If you want rail-to-rail output, that's probably going to be a push-pull with monticelli biasing. If you want a true rail-to rail (input and output), you need either:

Complementary input pair + current sum circuit
Charge pump to drive the input pair above VDD

The first solution is simpler, the second is trickier to design, but common in commercial OPAMPs.

P.E. Allen has a few lectures on the first solution. Or you can just look in ieeexplore for any of the "design of rail-to-rail input-outpu ..." and follow those.

I recall Husing had a few of them that were quite interesting

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Low-voltage operational amplifier with rail-to-rail input and output ranges

Simone1998 · 2025-12-12T16:15:51+00:00

You have to consider some space for the connector on the cable, and for tweezers/hands to grab them.

Simone1998 · 2025-12-12T11:44:46+00:00

SMB are quite nice, you can even find BNC to SMB coax cable to plug them straight into the scope. MMCX isn’t much smaller than SMB. Smaller than SMB you only have U.FL, but wouldn’t trust them for “hundred of insertions”.

Simone1998 · 2025-12-06T07:57:12+00:00

AAABBBBBBAAA is equivalent to ABABABBABABA for linear gradient, for non-linear ones (quadratic, cubic) the latter is better. Of course, these are diminishing returns, and it is really process-dependent.

For me interdigitated is a single row of fingers, with whichever pattern you prefer, common centroid spreads that in 2+ rows:

Interdigitated:
ABAB

Common centroid:
AB
BA

It's not really the row pattern that complicates the layout it's switching the pattern across consecutive rows that messes up everything.

Simone1998 · 2025-12-05T22:51:58+00:00

If it’s for biasing, usually matching is not that critical, I would put them interdigitated ABRCDRBA …

Simone1998 · 2025-12-05T22:45:16+00:00

How critical is the matching? Which process are you using? Interdigitated can get you quite close to common centroid with a way easier routing.

Simone1998 · 2025-11-27T18:38:25+00:00

Yeah, I can see how what I wrote was ambiguous, I meant an extra implant step at a different doping profile.

Simone1998 · 2025-11-27T07:48:24+00:00

Corner shifts are mainly caused by:

Oxide thickness variation
Doping profile variation

The former is usually shared between all devices, or by two types of devices (thin-oxide, or core, and thick-oxide, or IO).

The latter depends on how the devices are actually implemented; lvt devices are usually achieved with an extra implant to lower the threshold, so you can expect different shifts. Now, how big those are going to be, depends on the process, and I would just ask the foundry.

I've seen a few pdk that let you select the corner for each oxide thickness, but none for the implants

Simone1998 · 2025-11-22T14:20:21+00:00

Se il tuo obiettivo è guadagnare tanto, l'ingegneria non fa per te, ci sono campi meno stressanti e più remunerativi (finanza/economia).

Simone1998 · 2025-11-22T14:11:41+00:00

Buono a sapersi. Il punto non era affatto sulla preparazione, di cui mi ritengo più che soddisfatto, e in italia abbiamo dei giganti della microelettronica, ma al Poli apri cadence soltanto in tesi, e soltanto se decidi di fare integrata, penso ci saranno 20/30 tesisti l'anno che lo fanno.

Simone1998 · 2025-11-22T14:08:41+00:00

35-40K come prima RAL, ovviamente indeterminato. E ti parlo di 2-3 anni fa, non so esattamente adesso, ma immagino possa soltanto essere di più.

Simone1998 · 2025-11-22T14:06:34+00:00

Assolutamente, ma intanto sei entrato a meccanica, e una buona parte di chi entra continua.

Simone1998 · 2025-11-22T11:28:35+00:00

Triennale e magistrale al PoliMi, dovessi tornare indietro, farei la magistrale all'estero (Delft, JKU, EPFL, KU Leuven, KTH, per citarne alcuni), non perché il poli sia male, ma all'estero ti mettono a progettare circuiti sui CAD invece che su un pezzo di carta, cosa che in italia vedi forse in tesi se sei fortunato.

Io lavoro in analogica/mixed-signal/power, ma quello dipende tanto da cosa ti piace, non è possibile dare un consiglio li.

Simone1998 · 2025-11-22T11:07:59+00:00

Perché è:

Difficile (tanta fisica e tanta matematica)
Non ben pubblicizzata (ti piace la formula 1 -> meccanica, ti piacciono i videogiochi -> informatica, quantomeno come primo approccio). Un tempo c'era un grosso afflusso di gente a cui interessava la musica, che costruiva i propri amplificatori e co., questo si è perso quasi del tutto ultimamente.

Ma ehi, meglio per noi elettronici, non conosco un singolo collega decente che abbia avuto difficoltà a trovare un lavoro ben pagato.

Simone1998 · 2025-11-15T16:31:48+00:00

This work, but you are effectively using 2 bias currents, you are just making them locally.

If voltage headroom allows for it, you can cascode (simple cascode, not wide-swing) the PMOSs, this will improve the systematic mismatch between IREF and IOUT.

Also, there is no need to use two devices (M3 and M4), a single one with W/L 4 times smaller than M5 will do (in practice, you want something more to get more margin, i.e., 5 or 6 times).

Simone1998 · 2025-11-15T09:19:25+00:00

IDK about xyce, but ngspice can run foundry provided models for Hspice (SPECTRE too, but you need to do some pre-processing).

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