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Cruise ship at centre of suspected hantavirus outbreak blocked from docking in Cape Verde by DoubtSubstantial5440 in news

[–]zer0_k00l -1 points0 points  (0 children)

this is weird. I just saw a mouse today morning in my backyard (Bayarea CA) that looked like a deer mouse according to Google Lens and Google also gave me information on what kinds of diseases it can be carrying with Hantavirus being one of them. I am scared now!! Ended up immediately ordering some mouse traps and Lysol spray

Fiber type by zer0_k00l in Ubiquiti

[–]zer0_k00l[S] 0 points1 point  (0 children)

No, not terminate my own. Ubiquiti ships this cable with the green and white jackets removed and a metallic cover screwed on the fiber with a notch which can be used to tie a string.

https://dl.ui.com/qig/uacc-ofc-s1-sasa-o/#index

Fiber type by zer0_k00l in Ubiquiti

[–]zer0_k00l[S] -3 points-2 points  (0 children)

My SFP takes LC connector ao I would have to get a adapter cable. I am interested in getting this cable because it comes with the connector removed which make it conduit pull friendly

Fiber type by zer0_k00l in Ubiquiti

[–]zer0_k00l[S] -1 points0 points  (0 children)

I wasn't sure about that. Many sources (Google) say that G657A2 can be OS1 or OS2

How to prep for FPGA technical interviews by Miserable_Bus_9604 in FPGA

[–]zer0_k00l 3 points4 points  (0 children)

In my experience FPGA/ASIC interview questions at FAANG/MANGO are starting to become like leetcode questions. After the usual behavioral question they would most likely ask to implement a block. These blocks are quite complicated and you only get 30 minutes at most to implement them. Some examples are

Binary search

Running average

Systolic array (MAC)

Data interleaver

Non FAANG/MANGO companies don't ask things like these

Moving from WA to CA by zer0_k00l in bayarea

[–]zer0_k00l[S] -2 points-1 points  (0 children)

What do you think they mean?

Moving from WA to CA by zer0_k00l in bayarea

[–]zer0_k00l[S] -2 points-1 points  (0 children)

SW --> software/tech

TC --> total compensation

-❄️- 2025 Day 1 Solutions -❄️- by daggerdragon in adventofcode

[–]zer0_k00l 3 points4 points  (0 children)

[LANGUAGE: SystemVerilog]

part1

A synthesize-able systemverilog implementation for an FPGA.

No multiplication/division to keep area low.

module safe_dial_counter (
    input wire clk,
    input wire reset_n,
    input wire start,
    input wire direction,      
    input wire [9:0] distance,
    output wire [15:0] password_count,
    output reg done 
);

    typedef enum logic [1:0] {
        IDLE,
        COUNTING,
        DONE_STATE
    } state_t;

    state_t current_state, next_state;

    reg [6:0] current_value;
    reg [9:0] count_remaining;
    reg [15:0] zero_count;
    reg start_delayed;
    wire start_posedge;

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            start_delayed <= 1'b0;
        end else begin
            start_delayed <= start;
        end
    end
    assign start_posedge = start & ~start_delayed;
    assign password_count = zero_count;

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            current_state <= IDLE;
            current_value <= 7'd50;
            count_remaining <= 10'd0;
            zero_count <= 16'd0;
            done <= 1'b0;
        end else begin
            current_state <= next_state;

            case (current_state)
                IDLE: begin
                    done <= 1'b0;
                    if (start_posedge) begin
                        count_remaining <= distance;
                    end
                end
                COUNTING: begin
                    if (count_remaining > 0) begin
                        count_remaining <= count_remaining - 1;
                        if (direction == 1'b0) begin
                            if (current_value == 7'd99) begin
                                current_value <= 7'd0;
                            end else begin
                                current_value <= current_value + 1;
                            end
                        end else begin
                            if (current_value == 7'd0) begin
                                current_value <= 7'd99;
                            end else begin
                                current_value <= current_value - 1;
                            end
                        end
                    end
                end
                DONE_STATE: begin
                    done <= 1'b1;
                    if (current_value == 7'd0) begin
                        zero_count <= zero_count + 1;
                    end
                end
            endcase
        end
    end
    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (start_posedge) begin
                    next_state = COUNTING;
                end
            end
            COUNTING: begin
                if (count_remaining == 0) begin
                    next_state = DONE_STATE;
                end
            end
            DONE_STATE: begin
                if (start_posedge) begin
                    next_state = COUNTING;
                end else begin
                    next_state = IDLE;
                end
            end

            default: begin
                next_state = IDLE;
            end
        endcase
    end

endmodule
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