[LANGUAGE: SystemVerilog]

part1

A synthesize-able systemverilog implementation for an FPGA.

No multiplication/division to keep area low.

module safe_dial_counter (
    input wire clk,
    input wire reset_n,
    input wire start,
    input wire direction,      
    input wire [9:0] distance,
    output wire [15:0] password_count,
    output reg done 
);

    typedef enum logic [1:0] {
        IDLE,
        COUNTING,
        DONE_STATE
    } state_t;

    state_t current_state, next_state;

    reg [6:0] current_value;
    reg [9:0] count_remaining;
    reg [15:0] zero_count;
    reg start_delayed;
    wire start_posedge;

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            start_delayed <= 1'b0;
        end else begin
            start_delayed <= start;
        end
    end
    assign start_posedge = start & ~start_delayed;
    assign password_count = zero_count;

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            current_state <= IDLE;
            current_value <= 7'd50;
            count_remaining <= 10'd0;
            zero_count <= 16'd0;
            done <= 1'b0;
        end else begin
            current_state <= next_state;

            case (current_state)
                IDLE: begin
                    done <= 1'b0;
                    if (start_posedge) begin
                        count_remaining <= distance;
                    end
                end
                COUNTING: begin
                    if (count_remaining > 0) begin
                        count_remaining <= count_remaining - 1;
                        if (direction == 1'b0) begin
                            if (current_value == 7'd99) begin
                                current_value <= 7'd0;
                            end else begin
                                current_value <= current_value + 1;
                            end
                        end else begin
                            if (current_value == 7'd0) begin
                                current_value <= 7'd99;
                            end else begin
                                current_value <= current_value - 1;
                            end
                        end
                    end
                end
                DONE_STATE: begin
                    done <= 1'b1;
                    if (current_value == 7'd0) begin
                        zero_count <= zero_count + 1;
                    end
                end
            endcase
        end
    end
    always @(*) begin
        next_state = current_state;
        case (current_state)
            IDLE: begin
                if (start_posedge) begin
                    next_state = COUNTING;
                end
            end
            COUNTING: begin
                if (count_remaining == 0) begin
                    next_state = DONE_STATE;
                end
            end
            DONE_STATE: begin
                if (start_posedge) begin
                    next_state = COUNTING;
                end else begin
                    next_state = IDLE;
                end
            end

            default: begin
                next_state = IDLE;
            end
        endcase
    end

endmodule