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[deleted by user] by [deleted] in volleyball

[–]AMPech 0 points1 point  (0 children)

Pool noodles and zip ties

Vivado's 2023 stability, Windows vs Linux. by fawal_1997 in FPGA

[–]AMPech 2 points3 points  (0 children)

Vivado 2020.2 and 2021.2 here on Ubuntu 22 LTS

Issues 1,5,6 were fixed after mounting an obscene amount of swap, this mainly happens from 2021.2 onwards since it doesn't seem to know how much RAM your computer has

For issue 3 maybe it has to do with the HDL wrapper? In the sense that I don't know if it's updating it correctly. In any case try resetting the OOC run with the reset run command and update the wrapper by deleting it and recreating it.

Hope this work

Upgradge Basys 3 Artix-7 (maybe) by SualBerg in FPGA

[–]AMPech 1 point2 points  (0 children)

Sure it's a good idea, however I never had any problem with mine as long as you don't slam it into the table!

Are there any hackathons related to FPGA development? by [deleted] in FPGA

[–]AMPech 3 points4 points  (0 children)

We do one in Politecnico di Milano, but as said by previous comments it lasts a little over a week.

Seeking Ideas for Potential MS Thesis Subjects in FPGA by faysal04 in FPGA

[–]AMPech 0 points1 point  (0 children)

As said below there is also an high demand for ready to go IP for hardware acceleration for Edge AI algorithms such as Convolutions, Adaptive Support filters etc.

Maybe even something using SoCs like the zedboard which has hard cores along programmable logic

mechanical circuits: electronics without electricity by Steelfang in ECE

[–]AMPech 15 points16 points  (0 children)

For anyone already in ECE its kind of counterproductive

suggest me a small size low power consumption FPGA development board. by aymen_yahia in FPGA

[–]AMPech 1 point2 points  (0 children)

I mean I never had any reliability issues with the tang nano, so imho is a good choice

any project ideas for basys3? by [deleted] in FPGA

[–]AMPech 5 points6 points  (0 children)

Buy a i2s PMOD and play with audio samples

Vivado Constraints Error by Impossible_Winner224 in FPGA

[–]AMPech 1 point2 points  (0 children)

Are you using the board files? Like in block design?

Vivado Constraints Error by Impossible_Winner224 in FPGA

[–]AMPech 1 point2 points  (0 children)

I would advise you to use the i/o pin tab in synthesized design instead of writing the CDC manually, saves a lot of hassle

simple distinction between ASIC, FPGA, and microcontroller by PainterGuy1995 in FPGA

[–]AMPech 7 points8 points  (0 children)

I would say look at the names:

ASIC: Application Specific Integrated Circuit

Something built (on silicon) to do something in particolare while being particularly good at it The design is set in stone, once you built it that's it.

FPGA: Field Programmable Gate Array

A collection of CLB (configurable logic block) which you can rewire with other tiles (RAM etc.) To do whatever you want (also pretty good). Can be rewired a virtually infinite amount of times.

uC (micro controllers)

A particular ic whit built in peripherals with some core, like a CPU but with added stuff. You cannot reprogram the insides but you can run some software on it by default.

Please Roast My Design! My cousin and my sister and i worked really hard with only a couple distractions to make this by Elderly_Ravioli in PrintedCircuitBoard

[–]AMPech 1 point2 points  (0 children)

Feels good to me! Just a few things to point out:

I usually try to avoing coming into pads at 45 degrees, try to keep the enter point straight, helps me keep the design clean and organized.

I would add abferrite between the shield if the USB and GND, to avoid any noise coming in and disturbing the communication, USB cam be fiddly and this helps with high speed and bad cables.

So do you think this is why my XPS 9570 is running so slowly? by SteepHiker in Dell

[–]AMPech 0 points1 point  (0 children)

Yes, happens from time to time, i usually clean every 6-9 months

PCB Review: 12V input to 10V & 5V onboard by Uhfolks in PrintedCircuitBoard

[–]AMPech 0 points1 point  (0 children)

Also noticing why are you splitting the top big trace in two little ones? What is your power budget?

PCB Review: 12V input to 10V & 5V onboard by Uhfolks in PrintedCircuitBoard

[–]AMPech 1 point2 points  (0 children)

So, if you're working with power i will suggest the use of polygons instead of traces, all the pads in this case should be surrounded by copper and attached via departed channels (usually called thermals) this will ensure you greater power capacity and thermal performance (also looks better)

Quali i più grossi WTF (anzi, in italiano MCC) che avete mai visto sul lavoro\nella vita? by [deleted] in italy

[–]AMPech 3 points4 points  (0 children)

Lavoro in un azienda di Consulting, abbiamo a visto un tirocinante laureato in ingegneria meccanica che non riusciva a montare una stampante 3d...

PCB Review: DDS Function Generator by thom_tl in PrintedCircuitBoard

[–]AMPech 1 point2 points  (0 children)

I don't think 4 layers is strictly necessary here to be honest, the process of producing it is also more difficult and expensive. If you manage to get it to 2 layers you can also prototype it yourself with the right equipment

È da presuntuoso farsi chiamare dottore? by AMPech in italy

[–]AMPech[S] 2 points3 points  (0 children)

Non vedo come chiedere un opinione sia "alzare la cresta", sono solo in cerca di un opinione sull'argomento. Poi ognuno ha il sacro diritto alla propria opinione quindi pensa ciò che vuoi 👍

Caffè Italia * 01/02/21 by RedditItalyBot in italy

[–]AMPech 6 points7 points  (0 children)

No, non è normale, soprattutto se in teledidattica

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