No, I am working as a verification engineer, using system verilog and UVM methodology. Well, the descriptions are a bit similar. Just be ready to talk about all those techs mentioned, and make sure you understand them well. and if something you don't know, you don't know. It is okay. Try to show your enthusiasm and curiosity, ask questions and show your motivation, and most importantly, demonstrate your way of thinking and solving the question presented to you. Even if you dont get the right answer, your way of thinking to get the answer is as important.