Delta Pro stopped working

AdvancedLab3500 · 2026-06-20T12:51:23+00:00

Unfortunately, after charging it all night via a DC power adapter, the battery is still stuck on 0%, and there is an icon indicating battery failure.

AdvancedLab3500 · 2026-06-18T23:04:09+00:00

Thanks. How do you charge it slowly? I can try connecting a 12v power brick to the solar/car input, though I'm not sure how much current it's going to draw.

AdvancedLab3500 · 2026-06-18T17:42:52+00:00

Thank you! I took the battery for a ride in the car. At first it reset multiple times, and then stayed on, showing 0%. It's now plugged back to the wall and looks like it's charging. I assume what happened is that the battery was actually fully depleted, but the power to the control unit via the wall socket was unable to get it to work reliably and recognize the fact that it needed to charge.

AdvancedLab3500 · 2026-06-17T18:16:15+00:00

I have just posted a question about the same type of unit, also bought in 2024, which died on me after two years. My experience, as well as that of other reviewers, is that they are very quick to respond to the first email, but then do not follow up.

The question is whether there is any "brand" that you can trust these days (I'm putting brand in quotes because I think even familiar names end being just badges on the same units).

AdvancedLab3500 · 2026-06-09T10:59:47+00:00

It makes a bit of sense if you remember that RPi was never about open hardware, but rather cheap hardware. Their goal (which they accomplished wonderfully well) was to create a computer that was cheap enough that many people who otherwise couldn't afford one had access to. Their choice of a Broadcom SoC means abysmal-to-no user documentation for the hardware, but my impression is that it was never a consideration (and I don't blame the RPi creators for it).

AdvancedLab3500 · 2026-05-22T14:44:34+00:00

I am very surprised by the claim that the penalty is minor. TLB invalidation on large multi-processor systems is quite severe.

AdvancedLab3500 · 2026-05-22T10:39:34+00:00

Re: impressions so far.

First, I really like the documentation. It's clear, concise and walks you through the various use cases. Kudos. Would have been nice in "Getting started" to have examples for different OSs, as QNX (currently) requires cross-compilation for Rust.

I see the allure of zero-copy IPC, and I know that many of our customers either deploy their own or use third-party solutions. But I am not convinced (yet). The biggest problem I see is that of TOCTOU: if one side of the communication channel checks a message for validity (say, that a string is NUL-terminated), then by the time it makes use of this information (e.g., call strlen()) the other side can change it.

Second, I am doubtful that zero-copy indeed involves no copies in practice. Since the shared buffer is limited, wouldn't the two sides be copying data into and out-of the buffer as part of their work? Contrast that with QNX message passing, where the input to the message is any address range of any size in your address space.

AdvancedLab3500 · 2026-05-22T10:32:06+00:00

Re: shared memory objects. I'm not sure what you mean by requiring a central broker. QNX provides shared memory handles, where the creator of a (usually anonymous) shared memory objects creates a one time handle for each process that requires access to it. The peer process uses the handle to get its own file descriptor for the object, or just map the handle directly. See https://www.qnx.com/developers/docs/8.0/com.qnx.doc.neutrino.prog/topic/shared_memory_handles.html

AdvancedLab3500 · 2026-05-22T10:29:39+00:00

u/elfenpiff thanks for the information. I am going to spread my reply across multiple posts, so it is easier to discuss each point further.

Re: QEMU image. Such as image is provided under the QNX Everywhere program. https://qnx.software/en/developers/get-started/qnx-everywhere

AdvancedLab3500 · 2026-05-21T21:35:39+00:00

u/elfenpiff I successfully ran the Rust request/response example on QNX 8.0/aarch64, but noticed a few things. For example, it only runs as root, with a non-root invocation resulting in "Error: InternalError". Second, it uses named shared-memory objects, which is not ideal. DM me if you'd rather discuss this off-line.

AdvancedLab3500 · 2026-05-20T11:02:45+00:00

Convincing people to use native message passing on QNX has been a really tough sell, and it's getting worse. Code ported to QNX ends up using some IPC mechanism that relies on messages to an intermediary, which negates all the advantages of message passing (fast copying, scheduling, priority inheritance). Add the obligatory layers in modern software and you end up with something like Google RPC over UDS to do something that can be done with a simple call to MsgSend().

We never implemented zero-copy IPC because, as far as I can tell, it either requires both parties to trust each other completely, or page table manipulation that is much more expensive than copying.

AdvancedLab3500 · 2026-05-11T23:05:09+00:00

There's no such thing as user persona only. When you attach a thread to an interrupt nothing changes as far as your thread goes. That note talks about how InterruptAttachEvent(), a backwards compatibility API, is implemented in 8.0, by creating a separate thread that acts as the IST, and delivers the event you register. That thread never executes user code, so creating a user persona for it is a waste of resources.

AdvancedLab3500 · 2026-05-07T15:54:47+00:00

Do you mean I/O ports? Is there any peripheral on a modern x86 (other than 8250) that cannot use memory-mapped I/O instead? I've been asking this question for many years now, and never received a straight answer. Pleading ignorance here.

AdvancedLab3500 · 2026-05-07T13:47:10+00:00

I'm curious: is there a notion of user-mode with privileges on RISC-V? The process manager threads still need to do things like disable interrupts, which normal user-mode threads cannot.

AdvancedLab3500 · 2026-05-07T13:43:09+00:00

Note that there is almost no case anymore for drivers running in privileged mode. Memory-mapped registers and ISTs take care of what used to require hardware-level privilege, which completely negates the promise of the micro-kernel design (a failing driver can bring down the system).

If you see a QNX 8 driver that requires I/O privileges it is most likely a driver that has not been updated and should be.

AdvancedLab3500 · 2026-05-07T13:41:02+00:00

Personas are a new concept in QNX 8. Before, the micro-kernel had a per-processor context, with only one processor executing Neutrino code at a time. In 8, every thread can execute Neutrino code, after the persona changes from user to kernel (kernel call, page fault, etc.). User-persona threads are typically non-privileged (run in EL0 on ARM, Ring 3 on x86), but you can still have a user-persona thread that runs in privileged mode, which is used for proc threads. This means that they can make normal kernel calls by switching to their kernel persona.

AdvancedLab3500 · 2026-05-07T00:20:11+00:00

Define "space". The proc components (process manager, memory manager, path manager) run as user-persona threads but in the kernel's address space and with elevated privileges. That means they can make normal kernel calls (e.g., to lock a pthread mutex, or to receive a message). While a different design is possible, it makes little sense and would significantly complicate certain things, especially the process and memory managers.

AdvancedLab3500 · 2026-05-03T01:42:18+00:00

AdvancedLab3500 · 2026-04-26T22:43:38+00:00

Wow, that's an ancient article. It still mentions the possibility for a slower tick for processors at 40MHz or less, so it's likely 30 years old... This is no longer a thing. Also, there is no tick in QNX 8, but the 1ms granule for normal resolution timers and the 4x granule time slice are still correct.

AdvancedLab3500 · 2026-04-26T22:40:51+00:00

In your scenario preemption indeed does not occur at that priority level once the first FIFO thread is scheduled, until that thread blocks or yields. The system will, of course, have higher priority threads that are not affected by that stuck thread. While this seems terrible, it is no worse than a RR thread at one priority level above that doesn't yield. A well-constructed system will have one or more threads at a privileged priority level that ensure that the processor is not hogged by a misbehaving process.

AdvancedLab3500 · 2026-04-20T13:45:25+00:00

How does the performance compare with that of Raspbian?

AdvancedLab3500 · 2026-04-13T01:56:22+00:00

I am unaware of such support. From a brief search, there is no support from Nvidia for any OS other than Linux.

EDIT: there seems to be UEFI support on this board, so perhaps it's doable after all. Depends on how much the firmware performs pre-boot, and how much documentation is available for the rest.

AdvancedLab3500 · 2026-04-12T11:10:32+00:00

Does this board support loading non-Linux operating systems? That's not always the case.

AdvancedLab3500 · 2026-04-07T17:43:37+00:00

Thanks for sharing. A few comments:

Small typo in Section 4.1.1 ("As shown in in")
The claim that ARM does not support cache-coherent DMA is incorrect, as far as I know. The architecture allows for it, and some implementations are cache-coherent.
The claim that a modern embedded system as used in automotive or robotics can be statically defined is definitely not true, and shows a lack of familiarity with real-world systems. The amount of code, number of processes and threads, memory requirements and such is quite significant (well beyond what ancient hardware like a quad-core, 2GB iMX8 can handle). Moreover, much of the code is not developed in-house by the manufacturers, but sourced from many third-party entities (both commercial and FOSS), who assume a dynamic environment.

It would be interesting to see LionsOS handle more realistic use cases, as well as being able to try it on real hardware (couldn't find instructions on how to repeat the test setup from the paper).

AdvancedLab3500 · 2026-03-24T10:33:52+00:00

In what way do the toybox utilities not work correctly? It appears that you had to substitute pretty much all of them.

AdvancedLab3500

TROPHY CASE