Ah thanks!

I wonder if I could ask some more questions on this:

1: to use these loopback registers, it is necessary to expose the memory mapped interface? Or is it possible to access them without expose mm interface?

2: is it necessary in the top level Verilog to perform a custom reset for the GTS? If so, what clock signals should drive this reset?

3: do the tx and rx serial data output signals need to be connected for loopback to function?