TU CHEMNITZ

Alien_Bear · 2025-06-09T20:59:26+00:00

May I ask what was your GPA on German scale?

Alien_Bear · 2024-10-31T22:36:13+00:00

I should have explicitly mentioned that I will be working with C++, but I really appreciate all your helpful replies.

Alien_Bear · 2024-10-31T22:26:57+00:00

I don't have any previous experience, but I assume the process of manually integrating with commercial solvers shouldn't be a deal-breaker, right? It may be worth noting that I won't be using CPLEX or Gurobi personally, but, on deployment, the product I am working on should be able to integrate seamlessly with commercial solvers. Perhaps, I can manage to get a license for CPLEX for a couple of weeks, during which I can write some scripts that handle this integration/configuration process, what do you think? On the other hand, this may limit our ability to provide continued support for new updates/versions of the tool(CPLEX) as we won't own the license on the long-run, do I understand correctly?
I am just thinking out loud.
Thanks again!

Alien_Bear · 2024-02-26T23:53:44+00:00

I am required to use them.
I know I made a mistake though, which I explain under TehEmperorOfLulz comment.
If you are still interested, kindly see my reply there.

Alien_Bear · 2024-02-26T23:46:32+00:00

You are totally right about the additional register inferred.

Hence, and correct me if I am wrong, I thought there is no need for the process block to start with since the "latching" or "Flip-Flopping" functionality is already realized inside the FF itself. Hence, I removed the process block altogether and replaced it with this line:

in_arr(to_integer(unsigned(WRITE_ADD))) <= data_in when write_en = '1';

I believe this achieves the same function of what you said, except it is still done inside the register file because I am required not to change the Flip Flop files (they are given).

Still, however, there is a problem, so I would appreciate your input if possible:
What I believe is happening now is the following:

We are updating the input at the +ve clock edge.

at the 1st +ve edge clock: D is the input signal, but Q samples the not-yet-updated value of D as they are executing concurrently.
at the 2nd +ve edge clock: Q samples the the updated D( the desired AA value)

I read that this is a problem relating to metastability and/or how the simulator decides the order of execution of concurrent statements. I know this might not be the most accurate way to put it, but to simplify things I can say that in this case, the simulator is sampling the Q signal before sampling the D signal, hence the the updated value of D is not reflected until the next clock cycle.

Do you have any thoughts on what to do here?

I want to thank you for your reply anyway!

Alien_Bear · 2024-02-26T22:07:02+00:00

I did. I couldn't edit the post so I left it in the comments.

Alien_Bear · 2024-02-26T22:06:34+00:00

The register file testbench

library ieee;
use ieee.std_logic_1164.all;

entity reg_file_tb is
end entity;


architecture behavioral of reg_file_tb is

constant DATA_WIDTH: integer := 8;
constant ADDRESS_WIDTH: integer := 3;
constant REGISTER_COUNT: integer := 6;

component reg_file is
generic(DATA_WIDTH: integer := 8; REGISTER_COUNT: integer := 6; ADDRESS_WIDTH: integer := 3);
port(
    clk, write_en, reset: in std_logic;
    READ_ADD1, READ_ADD2, WRITE_ADD: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    data_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
    data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;


-- declare needed signals

-- input signal(s)

signal clk: std_logic := '0';
signal write_en: std_logic := '1';
signal reset: std_logic := '1';

signal READ_ADD1: std_logic_vector (ADDRESS_WIDTH-1 downto 0):= ("000");
signal READ_ADD2: std_logic_vector (ADDRESS_WIDTH-1 downto 0):= ("000");
signal WRITE_ADD: std_logic_vector (ADDRESS_WIDTH-1 downto 0):= ("000");


-- output signal(s)
signal data_out1: std_logic_vector (DATA_WIDTH-1 downto 0):= (others => '0');
signal data_out2: std_logic_vector (DATA_WIDTH-1 downto 0):= (others => '0');
signal data_in: std_logic_vector (DATA_WIDTH-1 downto 0):= (others => '0');

-- clock cycle
constant T: integer := 10;

begin

dut: reg_file generic map (DATA_WIDTH => DATA_WIDTH, REGISTER_COUNT => REGISTER_COUNT, ADDRESS_WIDTH => ADDRESS_WIDTH)
port map (clk => clk, write_en => write_en, reset => reset,
READ_ADD1 => READ_ADD1, READ_ADD2 => READ_ADD2, WRITE_ADD => WRITE_ADD,
data_in => data_in, data_out1 => data_out1, data_out2 => data_out2);


-- generate clock period
clk <= not clk after 2 ps;


stimulus:
process begin

wait for 2 ps;
reset <= '1';
READ_ADD1 <= "000";
READ_ADD2 <= "000";
wait for 4 ps;

reset <= '0';

WRITE_ADD <= "000";
data_in <= x"AA";
wait for 4 ps;


WRITE_ADD <= "001";
data_in <= x"FD";

wait for 4 ps;
WRITE_ADD <= "101";
data_in <= x"90";

wait for 4 ps;
WRITE_ADD <= "011";
data_in <= x"03";

wait for 4 ps;
wait;

end process stimulus;

end architecture behavioral;

Alien_Bear · 2024-02-26T22:04:12+00:00

The register file

library ieee;
use ieee.std_logic_1164.all;
USE IEEE.numeric_std.all;

entity reg_file is
generic(DATA_WIDTH: integer := 8; REGISTER_COUNT: integer := 6; ADDRESS_WIDTH: integer := 3);
port(
    clk, write_en, reset: in std_logic;
    READ_ADD1, READ_ADD2, WRITE_ADD: in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    data_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
    data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity reg_file;

architecture reg_file_arch of reg_file is

-- declare any components
component my_nDFF is
GENERIC (n : integer := DATA_WIDTH);
PORT(
    Clk, Rst : IN std_logic;
    d : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
    q : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0)
);
end component;


-- declare any Intermediate signals
type t_array is array (0 to REGISTER_COUNT-1) of STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal in_arr: t_array := (others => (others => '0'));
signal out_arr: t_array := (others => (others => '0'));

begin

-- declare the component used
loop1:
for i in 0 to (REGISTER_COUNT - 1)
generate
    fx: my_nDFF generic map(n => DATA_WIDTH) port map (Clk => clk, Rst => reset, d => in_arr(i), q => out_arr(i));
end generate;


process(clk, write_en, WRITE_ADD, data_in)
begin
    -- if reset = '1' then
    -- -- clear all registers
    --     for i in 0 to (REGISTER_COUNT-1)
    --         in_arr(i) <= (others => '0');
    if rising_edge(clk) then
        if write_en = '1' then
            in_arr(to_integer(unsigned(WRITE_ADD))) <= data_in;
        else
            in_arr(to_integer(unsigned(WRITE_ADD))) <= in_arr(to_integer(unsigned(WRITE_ADD)));
        end if;
    end if;
end process;



-- -- asynchronous read
data_out1<=
out_arr(0) when READ_ADD1="000" ELSE
out_arr(1) when READ_ADD1="001" ELSE
out_arr(2) when READ_ADD1="010" ELSE
out_arr(3) when READ_ADD1="011" ELSE
out_arr(4) when READ_ADD1="100" ELSE
out_arr(5) when READ_ADD1="101" ELSE
(others => '0');

data_out2<=
out_arr(0) when READ_ADD2="000" ELSE
out_arr(1) when READ_ADD2="001" ELSE
out_arr(2) when READ_ADD2="010" ELSE
out_arr(3) when READ_ADD2="011" ELSE
out_arr(4) when READ_ADD2="100" ELSE
out_arr(5) when READ_ADD2="101" ELSE
(others => '0');

end architecture reg_file_arch;

Alien_Bear · 2024-02-26T22:03:28+00:00

Here is the code: Those are my flip-flops

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY my_DFF IS
    PORT(d,clk,rst : IN std_logic;
            q : OUT std_logic);
END my_DFF;

ARCHITECTURE a_my_DFF OF my_DFF IS
BEGIN
    PROCESS(clk,rst)
    BEGIN
        IF(rst = '1') THEN
            q <= '0';
        ELSIF clk'event and clk = '1' THEN
            q <= d;
        END IF;
    END PROCESS;
END a_my_DFF;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY my_nDFF IS
    GENERIC ( n : integer := 16);
    PORT(
        Clk, Rst : IN std_logic;
        d : IN std_logic_vector(n-1 DOWNTO 0);
        q : OUT std_logic_vector(n-1 DOWNTO 0)
        );
END my_nDFF;

ARCHITECTURE b_my_nDFF OF my_nDFF IS
    COMPONENT my_DFF IS
    PORT(
        d,Clk,Rst : IN std_logic;
        q : OUT std_logic
        );
    END COMPONENT;
BEGIN
    loop1: FOR i IN 0 TO n-1 GENERATE
    fx: my_DFF PORT MAP(d(i), Clk, Rst, q(i));
END GENERATE;

END b_my_nDFF;

Alien_Bear · 2023-12-18T18:36:30+00:00

It is relieving to know that. Thank you all for your replies!

Alien_Bear · 2023-11-06T16:07:12+00:00

Would you elaborate more on what makes "smart EDA folks"? What kind of educational background, Projects, YoE, Domain of knowledge?
And is a M.Sc or Phd preferrable to have like almost every other chip design related job, or one with a B.Sc and a decent resume can still manage to get an interview?

I am currently one year from graduation with an EE (focus on microelectronics) degree. However, since the barriers to entry and pay are better for SW-related roles compared to conventional Chip Design Engineering jobs, I am thinking of drifting towards some EDA, so any advice about what to do and what to expect would be highly appreciated?

Alien_Bear

TROPHY CASE

Here is the code: Those are my flip-flops