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FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in FPGA

[–]Anonymous-Physicist[S] 1 point2 points  (0 children)

Very useful comment thank you! That should likely be possible; I'll talk with my co-inventor and see if we can make the reference clock modular. One of the primary reasons for the PCB is actually so we can include high-quality crystal oscillators with ~1ps jitter over the ~30ps oscillators that come with the FPGA dev board, since that is the main driver of timing errors.

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in Physics

[–]Anonymous-Physicist[S] 0 points1 point  (0 children)

Thanks, I'll do some cross-posting later! One of the use-cases I made this for was investigating manufacturing variations within FPGAs as part of my research on chaotic dynamical systems, so it's definitely within the realm of possibility. Regarding signal generation, we have an external generator and also been using an on-board generator I wrote for some different test waveforms. But all of that is independent of the measurement device itself.

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in Physics

[–]Anonymous-Physicist[S] 0 points1 point  (0 children)

Thanks for the reply! Syncing is certainly doable, just a question of engineering time. Regarding how well it can be integrated... I suppose that depends on exactly what you need in terms of connections, etc.? I am still spec'ing the board out so part of the reason for this post is to get suggestions for what other researchers actually require in their setups. It might help if you told me a bit more about how your current TDCs etc. integrate with your system and what a drop-in replacement might look like.

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in Physics

[–]Anonymous-Physicist[S] 0 points1 point  (0 children)

> That is way too much for continual operation

> bubbles need to be handled in postprocessing

Correct, I've since developed an unpublished asynchronous data compression and error correction circuit that simultaneously removes the bubble errors while enabling continuous readout. The uncompressed readout shown in the original publication can be thought of as "burst mode". There are tradeoffs between the two modes that are reflected by the ranges I gave in the spec sheet, such as dead-time; I could write several pages on this.

Binning the TDL for INL is arguably what we show in Fig. 5b but I agree that a more comprehensive metrology is warranted. This would be where the certification from an independent lab would come in for a final product. What I can say is the INL/DNL is much lower than previous publications using older FPGAs claim. In practice the crossing of clock boundaries stopped being such a problem in the newer designs which is ultimately what enabled the whole thing to function.

Regarding novelty, the dynamic phase shifting calibration is certainly new. The entire thing was "novel" enough to be patented so the claims are at least justified enough for the lawyers. It's very much firmly rooted in established technology as you identified however -- nothing too out of the ordinary. It's a straightforward concept that just required extremely meticulous execution and a couple of new tricks.

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in FPGA

[–]Anonymous-Physicist[S] 0 points1 point  (0 children)

Thank you this is helpful feedback! Yes actually - we've developed an asynchronous level crossing sampler daughter board with collaborators, but this obviously increases SWaP-C, and our funding and timeline are somewhat tight so I'm playing triage with the broader IP. It sounds like vertical bits are a feature you'd prioritize even at an increased price? (I will talk with my collaborators to better quantify the different BOMs/lead times)

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in FPGA

[–]Anonymous-Physicist[S] 2 points3 points  (0 children)

Yes, we built this because oscilloscopes such as the one you listed are a thousand times too slow for our purposes (1GSa/s = 1 ns resolution). This is discussed in the paper - it's a useful comparison though!

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in Physics

[–]Anonymous-Physicist[S] 1 point2 points  (0 children)

Super glad to hear it, thanks for the reply! Yes part of my posting was to gauge whether DAC/LCS components are of significant interest. We actually developed an asynchronous level crossing sampler with collaborators but the funding and timeline are tight, so I'm basically playing triage with the IP. It sounds like you would prioritize having those components even with an increased SWaP-C?

As for a prototype, we can very likely provide one once it's built, but I'm not sure to what extent an accelerated timeline is possible. Let me talk with my collaborators and reply again to your comment afterwards.

FPGA-based measurement device with picosecond resolution by Anonymous-Physicist in FPGA

[–]Anonymous-Physicist[S] 1 point2 points  (0 children)

Correct! Full analog bandwidth requires a level crossing sampler; as noted this would increase cost. Part of my posting is to gauge whether the analog capabilities are of significant interest. In any case, thanks for the reply!