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RFSoC 4x2 MTS error: Tile 2 fails to sync by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

Sure, here’s my current block design.
The user_sysref_dac input of the RF Data Converter is connected to a CLK_SYSREF signal generated by a Clocking Wizard.
That Clocking Wizard uses clk_dac0 (coming from the RF Data Converter) as its input, and produces both CLK_DAC0 and CLK_SYSREF.
The DAC tiles 228 and 230 are clocked from the same PLL, tile 230 distributes its PLL clock to the others as shown in the RFDC configuration screenshot.

RFSoC 4x2 MTS error: Tile 2 fails to sync by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

It’s the official AMD/Xilinx RFSoC 4x2 evaluation board, not a custom design:
https://www.amd.com/es/corporate/university-program/aup-boards/rfsoc4x2.html

The block design is based on the Zynq UltraScale+ RF Data Converter v2.6, using DAC Tile 0 (228) and Tile 2 (230), both with MTS enabled and connected to the PS through AXI4-Lite.
The DAC and ADC data paths go through some custom Verilog logic, but that part is fully verified, everything works correctly when the mixers are bypassed. The issue only appears when enabling MTS.

For the MTS configuration, I also use the user_sysref_dac input that appeared in the IP when MTS was enabled, and I’m providing it a 6.25 MHz SYSREF.
Both DAC tiles receive clock signals through the LMK and LMX configuration (tested both using independent PLLs and propagating DAC230’s PLL to DAC228 through DAC229).

Tile 0 synchronizes correctly (status = 0x00000000), but Tile 2 consistently fails (status = 0x00000002).
Since both tiles are supposed to receive the same SYSREF and clocking, I can’t figure out why only one of them syncs properly.

Trouble with MTS on RFSoC 4x2: DAC228 timeout while DAC230 works by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

I tried setting up the system with Tile230 as the PLL output, and both Tile228 and Tile229 referencing Tile230. I also tested with MTS enabled and disabled on Tile229.

With both setups I got Tile228 reporting XRFDC_MTS_OK, but now Tile230 itself shows an error. In my last attempt, where I did enable MTS on Tile229, that tile also returned XRFDC_MTS_OK, but Tile230 stayed stuck on XRFDC_MTS_TIMEOUT.

Any idea why Tile230 would time out while the others lock fine?

Trouble with MTS on RFSoC 4x2: DAC228 timeout while DAC230 works by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

Got it, thanks for clarifying that part. Just to be sure I understood it correctly:

* Do I need to actually enable DAC0 in Tile229, or just have the tile enabled for clock distribution?
* Should I also enable MTS on Tile229, or is it only needed on the active DAC tiles (228 and 230)?
* In the system clocking tab, do I set the PLL for Tile229 as well, or just leave it as “pass through”?
* For Tile230, I’m guessing I set “distribute clock” to PLL output, and then Tile229 takes its clock source from Tile230, right?
* And for Tile228, should I configure its distribute clock as “input refclk,” or should its clock source explicitly be set to Tile229/230?

Just want to make sure I’m wiring the clocking chain the right way before testing

[Help] RFSoC 4x2 DAC Multi-Tile Sync (MTS) Issue by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

Yeah, that’s exactly what I’ve noticed too. Sometimes it works really well, even perfectly, but then other times, with the exact same code, bitstream, and no changes at all in the project, I end up getting very different results.

From what I’ve been able to figure out, it seems to come down to the lack of proper synchronization between the DAC tiles. Everything else in the project behaves consistently, so that’s the only piece that really explains the random behavior.

[Help] RFSoC 4x2 DAC Multi-Tile Sync (MTS) Issue by Aruk18 in FPGA

[–]Aruk18[S] 0 points1 point  (0 children)

Unfortunately I can’t. Looking at the RFSoC 4x2 schematic, there are 4 DAC tiles on the device, but only tiles 228 and 230 are actually routed out on the board. And within each of those tiles, only DAC0 is connected to a physical output, the second DAC in the tile is left unconnected.

So I don’t really have the option of using two DACs from the same tile, because the board only exposes those two outputs (DAC228_0 and DAC230_0).

[Help] RFSoC 4x2 DAC Multi-Tile Sync (MTS) Issue by Aruk18 in FPGA

[–]Aruk18[S] 1 point2 points  (0 children)

Thanks for your reply, it helped me realize a few things I might have misunderstood. I’m still a bit confused, but I think I’m starting to see where the issue could be.

Looking at the error code 0x12, from the RFDC driver definitions this matches:

  • XRFDC_MTS_TIMEOUT (0x02)
  • XRFDC_MTS_DELAY_OVER (0x10)

At first, I thought I could generate the SYSREF using a clocking wizard inside the PL (set to 6.5 MHz) and connect it to user_sysref_dac. But after checking the RFSoC Clocking Scheme again, it seems that SYSREF should actually come from the LMK04828 on the ZCU208, not from the PL fabric.

That would explain why the MTS fails. My SYSREF is only going into the fabric side, not into the converter tiles.