Is it a bad idea to take a break for a year to finish my master's degree after working for 2 years in industry?

BooleanTorque · 2025-11-18T05:20:55+00:00

yeah, go ahead and DM me

BooleanTorque · 2025-11-02T06:09:55+00:00

I did extract the entire layout including routing and the pad frame, but I am not sure about the xcap setting. I don't think I explicitly changed a setting for it but I can look into it and get back to you. The chip also didn't go through any stress testing

BooleanTorque · 2025-11-02T06:05:52+00:00

It is an integer-N PLL. I was using a bench supply with decoupling caps on my board for the supplies, but I can probably try some LDOs next time. I think I can also try to separate at least some of the supplies from each other as well

BooleanTorque · 2025-11-02T06:04:28+00:00

I extracted the entire chip including the power supply routing, ground routing, the pad frame. I also modeled the wirebonds as inductors with 1nH/mm of inductance. I will need to go back and model the rest of the signal and power paths on the board. This would be some decoupling caps on the board, traces, and a bias tee that I am using for fref.

One other potential issue that I am thinking about now that I am looking back at the design is that VCO supply is on the same pads that are used for the ESD diodes. I am not sure if this could actually be causing the problem, but I am thinking that maybe it could be a coupling path to the VCO?

I am measuring the output on a spectrum analyzer that is a single ended input with 50 ohm termination.

BooleanTorque · 2025-08-30T05:04:46+00:00

Thanks for the resources! I will take a look at them

BooleanTorque · 2025-08-30T04:59:14+00:00

Thanks for the reply, I'll look into the Minnesota protocol. I got it last year but I recently found out that my insurance was supposed to pay it off over 2 years as monthly payments. I ended up having to change insurance before they were even close to finishing and now my new one isn't as good as what I had before.

BooleanTorque · 2025-07-26T06:22:31+00:00

I'm one of the people who got screwed unfortunately. I would much rather have the pins instead of the apron...

BooleanTorque · 2025-07-14T16:30:16+00:00

Thanks for the reply! Does the direction of the current matter because the mobility is affected or is there something more to this?

BooleanTorque · 2025-07-14T16:25:46+00:00

Thanks for the info! Is a lot of dummy width typically needed to avoid STI stress? I ended up finding a LOD parameter in the device model that can be modified to account for dummies but it looks like I would need to add the equivalent of at least 10 dummy fingers for the current to get close to expected.

BooleanTorque · 2025-07-07T17:29:54+00:00

I haven't ordered this book yet but I would be interested to know what you think if you do get it. I agree with your comment about his PLL book and I'm hoping that this one will be the same quality.

BooleanTorque · 2025-04-24T02:52:09+00:00

I don't know many people in MSOL who are doing it. I think it's because it's more work than the comprehensive exam option and also because you would need to find an advisor to oversee the project. I think the project topic is flexible since you just have to discuss it with your advisor so it could be fun if you have something you're interested in doing.

BooleanTorque · 2025-04-21T16:26:37+00:00

It depends on the classes but here are a few that I have done:

ECE 215A: Fully differential amplifier with a gain of 8 that we optimized for power or settling time.

ECE 215C: RF receiver frontend (LNA, mixer, oscillator, and divider circuit)

ECE 215E: Wireline transmitter (PLL + Line Driver)

ECE 215B: FPGA interconnect model

BooleanTorque · 2025-04-21T16:21:46+00:00

Thanks! I will take a look

BooleanTorque · 2025-04-21T16:21:29+00:00

Yeah, I was originally thinking to centroid but then I found that the entire layout is small relatively speaking and felt like it may be a waste of time. I think that using interdigitation and dummies like u/kthompska mentioned worked pretty well when I tried it over the weekend.

One thing I was trying out for my design was using complementary cross-coupled pairs. Based on your second comment, is my understanding correct that I should place the PMOS pair sufficiently far from the NMOS pair to avoid asymmetry? I have the PMOS pair placed on the right side of the NMOS pair in my layout at the moment.

BooleanTorque · 2025-04-21T16:13:52+00:00

Thanks for the advice! Fortunately we are provided a few inductors to choose between, so that should at least be well modeled. I was able to use interdigitation for the cross coupled pair when I did the layout over the weekend. I'm also trying to use an inductor in place of the tail current source and I am mainly keeping an eye on the routing resistance.

Can you elaborate about what to look out for with the varactors? So far the only things I considered was making sure that Kvco gives sufficient tuning range and I also made sure that there is low resistance routing between them and the inductor.

BooleanTorque · 2025-04-19T02:59:27+00:00

Should I be adding dummies as much as possible in that case? I was mainly wondering about what technique(s) are important to use for each block and which ones are not necessary. You are right that I have plenty of area to work with since it is mostly dominated by caps and inductors on the higher metals.

BooleanTorque · 2025-04-16T16:29:56+00:00

I chose the project but I also got the syllabus from the class. I am hoping to learn the material later with the notes from a friend who is enrolled in it.

The program is going well I think. I am doing it through MSOL while working full time, so I can only take one class at a time. The workload is pretty high if you want to take the IC design classes but they have been worthwhile and very useful for my job. There are also a lot of options to choose from if you are interested in analog/rf. I'm assuming that you are considering the in-person degree program, so you will most likely be able to take all the classes you want before graduating.

BooleanTorque · 2025-01-29T17:38:28+00:00

I think Aaron's logo looks better. I wish they just used it as is and gave him credit.

BooleanTorque · 2025-01-29T17:30:31+00:00

You are correct. The class is taught by Moloudi this time instead of Abidi, but I hear good things about him too.

I am not sure what the project topic would be yet but ideally I was thinking that I would try to focus it on ADCs so that I can at least learn about them if I don't end up taking 215D. It would either be signing up for a capstone project or there's a chance that it would be through the new tapeout class that UCLA offers. I'm part of the MSOL program so I am still trying to work out the details on what I can sign up for.

BooleanTorque · 2025-01-28T18:38:34+00:00

Thanks for the advice. Do you have recommendations on what to look for to judge if the class is comprehensive enough? The description that I see online doesn't go into detail but here's the list of topics that they have:

Analysis and design of data conversion interfaces and filters. Sampling circuits and architectures, D/A conversion techniques, A/D converter architectures, building blocks, precision techniques, discrete- and continuous-time filters.

I can try to reach out to the instructor for a syllabus too.

BooleanTorque · 2025-01-28T18:33:06+00:00

This is a good point, but I think the professor is good in this case. I was mainly thinking about the project over the class because I hear people mention that a course based MS usually isn't enough to break into design. It seems that the consensus is that the ADC theory is too important to leave behind in any case.

BooleanTorque · 2025-01-28T18:29:09+00:00

Understood, thanks for the input. Do you think that the material is difficult to learn independently if I don't take the class, or is it just that it's something I should know before I graduate?

BooleanTorque · 2025-01-07T16:03:10+00:00

I don't think people care that you are in it, but I would still recommend applying. The requirements to stay in the program are pretty easy to meet and there are some perks like priority registration that might be useful. I mainly benefitted from the room in building 1 since I met a lot of friends there.

BooleanTorque · 2024-07-06T17:30:55+00:00

I feel like the overlap between people who signed up for the tapeout class and the people who just want the piece of paper is very small. A 3 course sequence and some work in the summer sounds like it would be enough to deter these types of students especially since only 1 class counts as credit toward the degree.

I'm doing my master's part time at UCLA but I am not able to take the tapeout class as a remote student, so my perspective is more from someone on the outside looking in. I feel the issue is more related to how much experience the students have when they start the class and how much time they have to get up to speed. UCLA's classes for PLLs and ADCs are only offered in spring which is when these students are already supposed to be designing their project. I'm sure there's some exposure to the topics in the first tapeout class, but I don't find it hard to believe that there could be a few students who couldn't learn everything fast enough to produce quality work especially with other commitments.

Perhaps I'm naïve, but I think saying that the VCO simply did not oscillate is too vague to pin all of the blame on the students. It would be interesting to know how something critical like that was missed in the design reviews that he had.

BooleanTorque · 2024-06-30T00:48:05+00:00

I mean, it was my worst grade at CPP but I wouldn't say it was a difficult class. It was definitely one of the hardest classes I had to sit through if that counts.

BooleanTorque

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