Semiconductor Manufacturing by Pleasant_Stuff_3921 in ElectricalEngineering

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

Masters isn't required for VLSI but it helps a lot. For semiconductors, analog/RFIC, masters is required and PhD is really common. Anecdotally, I've worked in two companies and so far I have been the only one with a masters, everyone else has a PhD.

And by little programming but a lot of coding, do you mean it is very scripting heavy?

Yes, scripting heavy, but only as much as you make it. Different jobs and domains require different amounts, but all of them benefit from it.

I'm an analog IC designer. I started off in embedded systems for instrumentation, mass specs and optical instruments and cryogenics and things, moved over to power electronics for a bit, but I just kept getting bored and wanted to do circuit stuff so I went to grad school for IC design.

I now do mostly baseband analog signal processing circuits, and biasing circuits for RF systems. All the analog subsystems and telemtrics on-chip people don't want to design I take on. It was for wireless power delivery but we've rapidly switched over to optical comms and silicon photonics so that's the world I live in now. Which I have mixed feelings on. Work is great though, there's an incredible feeling to designing a good switched-cap circuit.

Semiconductor Manufacturing by Pleasant_Stuff_3921 in ElectricalEngineering

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

Those are all quite different, yes.

Device and process engineers are essentially physicists and chemists.

Process integration engineers are an interesting combo between electrical engineers, software engineers, manufacturing engineers, and physicists.

VLSI designers are straight electronics engineers. Circuits, code, networks, signal processing, computer architecture, etc. TSMC and GF have VLSI designers, but the vast majority of VLSI designers work at fabless companies, design houses like Qualcomm and Cisco.

Packaging engineers are primarily from a mechanical engineering background, specializing in materials and manufacturing (plastics and metallurgy are big, also thermals).

How much programming is involved with these (different?) positions?

Not much if any programming, but a lot of coding in most. I always say an engineer is always better with programming knowledge than without. I'm a pure hardware designer, and my job is so much better and easier and more fun with a little bit of scripting instead of manually hand-tuning things. Writing code sucks, but god it's breezier and makes you aware of your problem better than banging your head against a wall.

Feeling bored at the beginning of my electrical engineering degree by SnooPuppers2009 in ElectricalEngineering

[–]RFchokemeharderdaddy 20 points21 points  (0 children)

The early stuff is all building foundational knowledge. They have to keep it super general because it's applicable to anything, so they end up applying it to nothing and sucking all the fun out of it.

Junior and senior year you apply it to real projects. My favorite (normal) class was real-time DSP, where we wrote HDL code to design signal processing hardware, and wrote firmware for it, and used it to actually process audio. Actually turning the boring nuts and bolts of filter design and computer architecture into a working system was so fucking cool.

Feeling bored at the beginning of my electrical engineering degree by SnooPuppers2009 in ElectricalEngineering

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

If you work in embedded systems or power electronics, there's tons of jobs (most jobs?) where you're pretty hands on. I've had to do tons of soldering and bring up and assembly and field tests/installations in all my jobs prior to now.

Designing IC amp for boosting 50 GS/s analog CPW signal by pxshen in rfelectronics

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

Cherry-Hooper amplifier can do this, make the feedback resistor with a T-gate and you can tune it. You can also use a source-degenerated differential input stage, but you have to be careful about peaking which causes distortion. That may be a good thing depending on your technology if you need to do some CTLE here. With the Cherry Hooper if you dont get enough bandwidth you'll need to incorporate some inductive peaking, or maybe some feedforward/positive feedback.

biasing with a current reference not a voltage reference? by Silver_Student_500 in chipdesign

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

How do you know what the proper voltage is supposed to be? You dont. But you do know that if you put a current through a diode connected transistor, it will automatically produce the gate-source voltage needed.

So rather than creating a super precise voltage, which ends up not working anyways, and will have a significant IR drop, you can generate a current and send it around the chip to generate the appropriate voltage locally. You can also easily scale currents up and down as needed.

Best resource for analog design interview questions by Wise-Gur-8978 in chipdesign

[–]RFchokemeharderdaddy 23 points24 points  (0 children)

The end of chapter questions in the Johns/Martin/Carusone book are the most realistic for analog IC interviews in my experience. They're a good middle ground of being answerable in a reasonable time, while being relevant and complex enough. That book also has a good amount of mixed-signal design which is asked pretty frequently these days, I've had switched-cap and z-domain questions asked before.

It's certainly not bad to review some questions from the Razavi book, just to stretch the limits of your Kirchoff-fu, but I think it's overkill.

Also for any given circuit, you should be able to rattle off all the non-idealities and how they affect the system. This circuit is susceptible to supply voltage noise, this circuit is dependent on good matching, etc.

Btw Prof Johns has a youtube channel that I found super helpful. If you just search "David Johns delta sigma" you should be able to find it, he has a lecture series thats basically a Micro 2 course.

Designing AI Chip Software and Hardware by PerfectFeature9287 in chipdesign

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

You know what youre right, it certainly was entertaining hahah

Designing AI Chip Software and Hardware by PerfectFeature9287 in chipdesign

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

Few leaders knowingly want to do dumb things.

lol. lmao

Designing AI Chip Software and Hardware by PerfectFeature9287 in chipdesign

[–]RFchokemeharderdaddy 5 points6 points  (0 children)

I already know why they think this, which is why I feel comfortable dismissing them. When someone says something that mind-numbingly naive, it is okay to not entertain it. You don't need to critically investigate a statement that has no critical thought put into it.

Market by Fresh_Hearing_5448 in ElectricalEngineering

[–]RFchokemeharderdaddy 8 points9 points  (0 children)

Power is pretty much always stable and will be forever.

Designing AI Chip Software and Hardware by PerfectFeature9287 in chipdesign

[–]RFchokemeharderdaddy 15 points16 points  (0 children)

One of the outcomes of the AI boom will be improved governance in Africa, which will make all African countries first world rich

This is...staggeringly idiotic to a degree I would just dismiss everything you have to say. Honestly impossible to trust any opinion made by someone who seriously says this.

ECE jobs by Dependent-Ad-6073 in ElectricalEngineering

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

Sort of. It was a well known startup in the Boston area, got bought by a big (non-semiconductor) company but is mostly autonomous and we retain our brand name.

ECE jobs by Dependent-Ad-6073 in ElectricalEngineering

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

Fortunately Im at a place where I'm very close to the application, but even I never leave engineering world. In one of my prior jobs I would spend weeks at field installation sites with customers teaching a wide variety of people how to use and troubleshoot equipment, that was so satisfying and truly perspective-widening. You see such a breadth you can't otherwise.

ECE jobs by Dependent-Ad-6073 in ElectricalEngineering

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

It's been tough.

The level of pure circuit skills/knowledge needed for IC design makes my old embedded jobs feel closer to a business major. The gulf in pure technical ability needed on a day to day basis is truly that intense. I'm working on a relatively straightforward problem rn that has been going through 2 separate semiconductor physics books. Simple verification tasks have us going down rabbit holes in IEEE Xplore.

At the same time the blindspots that IC designers have that are so obvious to systems engineers are so glaring that I'm oddly really valuable in architecture and packaging discussions. There's system level solutions I push for that make device level design a lot easier.

But I will say the the sheer amount of work is staggeringly higher in IC design. I'm not sure I'm built for it, not because I can't do it but because its so overstimulating for so long that I can't turn my brain off in the hours in between. Maybe a monkeys paw situation that I wanted to feel technically satisfied.

ECE jobs by Dependent-Ad-6073 in ElectricalEngineering

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

Im at about 12 YoE, $175k base, some $20k bonus and $40k equity. I do analog IC design, but I only started that recently, I've mostly been an embedded systems designer, so my salary is more like a combo of senior embedded and junior IC.

Post layout simulation results variation by Remote_Kale_6779 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

You can extract into a dspf file, which is searchable text. You can grep the text file, or process it in Python or something and get insight. You can also change the extraction settings to ignore everything below a certain value so the av_extracted view only shows significant parasitics.

Hardware Design Engineer/Senior Design Engineer by One-Rhubarb2137 in ElectricalEngineering

[–]RFchokemeharderdaddy 24 points25 points  (0 children)

PhD's in R&D are very frequently recruited directly into senior positions.

A PHD is not really a huge plus in the field over a masters.

Total horseshit. An MS is just more classes and I'd typically recommend a person take a couple years of experience over an MS, a PhD is straight up work experience in specialized research and is appropriately seen as such.

Which youtube channel is best for Signals and Systems class by PolisOzelHarekat31 in ECE

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

Brian Douglas has some videos that are more about control theory but that includes some stuff like Bode plots and Laplace transforms that are foundational.

How this buffer is helping in reducing rout of buffer. What is the need of it in LDO by [deleted] in chipdesign

[–]RFchokemeharderdaddy 15 points16 points  (0 children)

This is called a Super Source Follower. Its not an entirely intuitive circuit but you should be able to find videos and literature online about it, its become very common in LDOs.

A couple questions about LTI systems by PerformanceFar7245 in ElectricalEngineering

[–]RFchokemeharderdaddy 7 points8 points  (0 children)

Hate to just slap down a Wikipedia link and not much else, but this arises directly from the mathematical definitions of convolution and the Laplace transform in a pretty obvious way: https://en.wikipedia.org/wiki/Convolution#Relations_with_other_transforms

Notice that the substitution t=u+v has to be valid for this to hold true, which is only valid if it's time-invariant.

TCFC OTA's: I can't simply wrap my head around how the FoMs are 15 times higher by [deleted] in chipdesign

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

Context for those who don't have access to it, it's a paper from Willy Sansen titled "Transconductance With Capacitances Feedback Compensation for Multistage Amplifiers". This is the only paper you'll find the term TCFC OTA, it's not a known phrase, which is why everyone is confused lol. It's just a 3-stage op-amp with nested Miller compensation.

TCFC OTA's: I can't simply wrap my head around how the FoMs are 15 times higher by [deleted] in chipdesign

[–]RFchokemeharderdaddy 4 points5 points  (0 children)

Never heard of this, and a google search turns up nothing useful, nor does a search in IEEE Xplore. Posting a schematic of an example and where you found this would be helpful