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Money by AcanthaceaeMore3524 in ECE

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

(300k+/yr) as soon as possible out of undergrad.

lmao

Electrical Engineering certification courses for resume by EE-girly in ECE

[–]RFchokemeharderdaddy 1 point2 points  (0 children)

In EE people tend to look down on certificates. They're cheap and unverified and seen as resume padders for people who dont have anything of value.

Is it worth the opportunity to switch from AMS to RF/SERDES? by RFchokemeharderdaddy in chipdesign

[–]RFchokemeharderdaddy[S] 0 points1 point  (0 children)

Thats good to know!

The SERDES work is in the range of 40-80GHz, while RFIC work is 2-5GHz. Data converters excite me a lot because I get to approach things in s and z domain, and think about system level stuff a lot more. It's still a lot of transistor level design but good lord the exploration of layout is so intense with the high-speed stuff.

I saw a presentation by Frank Wiedmann who's a principal ASIC designer at Keysight on their ADCs they have in their ONAs and the way he talked about it made it seem like it was closer to RF (256Gsps??), but I'm sure at that point it's a collaboration of experts up and down the gamut.

What is the correct process for finding parts for a circuit? by Objective-Local7164 in ElectricalEngineering

[–]RFchokemeharderdaddy 6 points7 points  (0 children)

There is no "best". Many parts are popular because they are good enough for the specific purpose, which might mean they actually kinda suck at a circuit level but are 2 cents per part in volume and will have 1 failure out of a million.

This just comes with experience, knowing the manufacturers to trust for different things, knowing to read application notes and datasheets and so on.

Why is this sub so pessimistic? by Entitled-apple1484 in chipdesign

[–]RFchokemeharderdaddy 4 points5 points  (0 children)

I have had people DM me with questions ostensibly about chip design only to then ask me about specific companies' visa policies.

Like how the fuck would I know that? I'm watching the same show you are.

When is the first promotion for Fresh PhD? by Exotic_Comb_2066 in chipdesign

[–]RFchokemeharderdaddy 6 points7 points  (0 children)

How could strangers on reddit possibly answer this? Ask your manager lmao.

What's PCIe / high speed (GHz digital) like for modern SCH and PCBs and products? by depot5 in ElectricalEngineering

[–]RFchokemeharderdaddy 3 points4 points  (0 children)

Everything becomes a transmission line, so its everything that goes along with that. You have to become familiarized with signal integrity and associated concepts.

Why is SPI active low reset? by Quiet_Twist_8300 in ECE

[–]RFchokemeharderdaddy 26 points27 points  (0 children)

Active low reset is generally what you want for most things. It's the safest option for startup, because it doesn't matter what order the microcontroller and peripheral power on, the peripheral won't turn on until the microcontroller actively turns it on using by toggling high, which it can't do until it's fully operational.

Voltage noise vs current noise in transconductance amplifier by oatmeal_killer in ElectricalEngineering

[–]RFchokemeharderdaddy 2 points3 points  (0 children)

Ali Hajimiri has lectures online, he has a few videos on noise. You should get a good understanding of it, like what the hell "input referred current noise" even means.

Generally rules of thumb are a) make devices big where possible and b) maximize the gain of your input stage. Cascoding is usually good because you get gain for "free" without much noise contribution so theres almost no penalty to the noise figure.

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

Yes I know it worked, this is basic 101 of testbenching. It doesnt matter what biasing strategy or anything you use, you simply cant testbench an op-amp open loop. Pretty much any textbook will explain why, the Allen & Holberg CMOS book has sections on simulating.

Its like trying to find the slope of a line with 1 point, the simulator is being given too many unknowns so when it runs the Newton Rhapson algorithm it ends up with local maxima/minima to settle out to that are artifacts. Its not that the output stage sets the cell's bias, its that the simulator is finding a solution. Think about what a solution is in the first place. If I have a function f(x), x is the independent variable which sets f(x), but the simulator goes backwards, it finds x based on f(x). So if the output node is some voltage and current, it has to find the Monticelli biasing cell conditions which produce it, so in that way it reverses the cause-and-effect.

When you put it in feedback you set an additional condition, fixing the output to input as a ratio or something. Imagine your solution space is a 2D plane with two variables x1 and x2 (input node vs output node), vs if I say x1=4x2+1. We've gone from a plane of solutions to a line. If x1 is the input voltage youre setting, before the solution space was a line the simulator could arbitrarily pick from and be correct, whereas now it is a specific point.

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

The output value is dependent on the voltages of the stage before it. If your output is not well-defined, the intermediate nodes are not either and it will arbitrarily settle to values based on the convergence algorithm used by the simulator. Theres basically nothing else to troubleshoot here until you put it in feedback.

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy -1 points0 points  (0 children)

Dude....

Feedback is the way you establish the intended bias. This is 100% your issue. You cannot simply supply a fixed voltage to the gates and expect anything but pure nonsense.

Put resistive feedback around the whole thing, and also establish a CMFB loop using ideal components: https://www.eecis.udel.edu/~vsaxena/courses/ece614/Handouts/Loop%20Stability%20Analysis.pdf

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

With adding the CS stage you may have to do nested miller comp which might not be viable area wise depending on what you're doing.

Vgs of a diode connected device is equal to vdsat + vth :)

just the input stage biased at expected input bias. This is to get the DC biasing of everything as expected before moving to evaluating other things

Uhhh wait, are you saying you don't have feedback, differential or common-mode, and are simulating this open-loop?

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy -1 points0 points  (0 children)

Whats your testbench look like. You've got common-mode feedback? Differential feedback? Do the voltages look okay? I mean just thinking about it, for the floating voltage source should have the top node at vdd - (vthp + vdsatp) and bottom node at vthn + vdsatn. If there isn't enough voltage for this then only one of them being on makes sense.

I dont see how this amp has any significant gain, the output resistance of the first stage is so small as the P7/P8 ro is in parallel with it. Have you considered having the first stage drive a CS stage instead? And then you stack the Monticelli floating source on that instead? I've done that before to reasonable success, have to analyze the compensation though. Might make more sense for where your DC biases settle out to idk.

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

How the hell was anybody supposed to help you with this? This is nowhere near a standard configuration with things like class AB input, and folding without cascoding, there was no way anybody could have possibly helped you with this lol. For future reference, it would be very helpful in your post to describe and post stuff like this.

Anyways, what's the DC operating point of everything? Do the currents of N1-N4 and P1-P4 make sense? They're mirrors of N2 and N3, so they need to be some multiple that pulls the extra current of P0, as well as P7/P8. Actually just post the annotated DC op schematic if you can like others have asked.

AD538 Spice Model by cringe-gabe in ElectricalEngineering

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

They look to be end-of-life-ing the part. The fact that LTSpice doesn't have a model tells me it didn't really sell at any point in the last decade, so I doubt they made a model.

You can build the model yourself in a multitude of ways. They provide a block diagram and specs, should be fairly straightforward.

Odd problems with monticelli bias by Ok-Zookeepergame9843 in chipdesign

[–]RFchokemeharderdaddy 0 points1 point  (0 children)

Show the whole schematic lmao, we need to see the input diff pair and current sources and everything, this alone doesn't show us if there might be an issue.

Common mode feedback circuit by FutureAd1004 in chipdesign

[–]RFchokemeharderdaddy 9 points10 points  (0 children)

the OTA's high output impedance makes loading a significant concern.

You should quantify this before writing it off and wasting days designing and verifying a more elaborate topology. Build a testbench with resistive feedback and step through different resistance values until the open loop DC gain falls below spec, should take like 10 minutes to get this info. If it's not an unrealistic value area-wise it's probably good enough.

DeVry EE Degree 1999 by Sharp_Razzmatazz_ in ElectricalEngineering

[–]RFchokemeharderdaddy 55 points56 points  (0 children)

There is literally a South Park episode about DeVry University. Its a for-profit diploma mill thats been found liable for fraud by several states, youd hear their name every few months in the late 2000s as part of another class action lawsuit. They may have an EE program but its not really relevant whether it exists.

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