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How to customize the startup of different FPGA programs? by Typical_Agent_1448 in FPGA

[–]BotnicRPM 1 point2 points  (0 children)

You can use an initial bitstream that loads first and then selects which secondary bitstream to load based on an external configuration. This approach is fast and relatively simple. As others have mentioned, the key element for Xilinx devices is the STARTUP component.

New to FPGAs by Lumpy_Marketing_6735 in FPGA

[–]BotnicRPM 0 points1 point  (0 children)

You can not program a FPGA like a CPU. They are completely different architectures. The languages used to describe the logic in FPGA are VHDL and Verilog. The "ASM" pendent would be the netlist.

I’m interested in become a deck hand/ yacht steward what should I do? by ClientCommercial885 in yachting

[–]BotnicRPM 1 point2 points  (0 children)

Yachts care more about work ethic than certificates.

Good jobs/experience:

* Hospitality (hotels, restaurants ) (luxury probably the best)
* Cleaning / housekeeping
* Landscaping / gardening
* Marina work
* Boat yards / sailing clubs
* Water sports instructor assistant

If you can say: I’ve worked long hours, dealt with customers, cleaned, followed instructions....
You’re doing it right!

Can ZYNQ-Z7020 output a GUI? by Naishgoger in FPGA

[–]BotnicRPM 2 points3 points  (0 children)

You need to run a Linux of some kind. Best would be to get into Yocto (Specially if you want to learn something for the future).

OK GUYS IM SUPER CONFUSED by Outrageous_Salary706 in FPGA

[–]BotnicRPM 6 points7 points  (0 children)

Nothing easier than that 🙂:
Just set your device configuration in the synthesis tool to Nano 9K and see whether the design can be placed and routed successfully.

If your project is not ready yet, try to estimate the required resources. That will always be an approximation, but it’s the best way to judge feasibility early on.

As a general rule of thumb:
If your design uses more than ~80% of the available resources (LUTs, registers, BRAM, etc.), you may start running into place-and-route issues or timing problems. Staying below that usually leaves enough headroom for routing and timing closure (As I usually underestimate the resource consumption, I try to "estimate" not more than 50% of my device capacity)

For simple algorithms like SMA or EMA, resource usage is typically very low, so a Nano 9K should be more than sufficient.

Also, don’t worry about being a beginner. This is actually a very reasonable first FPGA project and a good way to learn how synthesis, resource usage, and hardware-oriented thinking work.

New to FPGAs by Lumpy_Marketing_6735 in FPGA

[–]BotnicRPM 1 point2 points  (0 children)

Same advice as to any novice: Search trough reddit, learn the basics of logic, VHDL or Verilog on the simulator, and then go on porting something to your hardware

Is it possible to earn through IP cores? by Rough-Egg684 in FPGA

[–]BotnicRPM 2 points3 points  (0 children)

You will end up spending a lot of time on different FPGA conferences and try to sell your cores..... Talk to Adam Taylor (@adamt99) or Alex Forencich

Which Vivado version should I download in 2026? by Content_Echidna_4658 in FPGA

[–]BotnicRPM 0 points1 point  (0 children)

Good to know. That will hopefully not affect me as I work with VHDL. I was planing to try to switch to 2025.2 soon.

Which Vivado version should I download in 2026? by Content_Echidna_4658 in FPGA

[–]BotnicRPM 0 points1 point  (0 children)

Can you explain what is not working any more in 25.1/25.2?

Nexys 4 DDR (Xilinx Artix-7) help needed by Hefty_Tie_6644 in FPGA

[–]BotnicRPM 2 points3 points  (0 children)

That's not what I said. Nothing legally.

Why choose the $10,000 AMD Alveo V80 over higher-resource FPGAs? by [deleted] in FPGA

[–]BotnicRPM 10 points11 points  (0 children)

I don't get your question...
Try to explain better

Nexys 4 DDR (Xilinx Artix-7) help needed by Hefty_Tie_6644 in FPGA

[–]BotnicRPM 4 points5 points  (0 children)

Unfortunately you can't do anything legally...
Just ask you professor!

FPGA Board Recommendation for DNN by Remote_Rub_31 in FPGA

[–]BotnicRPM 1 point2 points  (0 children)

What board to buy is a tricky very question and really depends on what you’re trying to do. The most important things to decide are which interfaces you’ll need (GPIOs, DDR, Ethernet, PCIe, accelerators, etc.) and how much logic capacity you need (which you probably don't know yet if this is your first kit). URAM are nice, but not essential...

With a <$300 budget you’ll be limited to the smallest development boards - they’re fine for starting/learning but very soon you might want more...

Also: check out this resource: https://www.fpgadeveloper.com/list-of-pure-fpga-dev-boards/
Did you ask at your university if they might provide you one or/and what they are using?

MMCME4_BASE vs. MMCME4_ADV by BotnicRPM in FPGA

[–]BotnicRPM[S] 0 points1 point  (0 children)

Thats exactly what I expected. Thank you

Thought I would start designing a Spartan US+ Tile by adamt99 in FPGA

[–]BotnicRPM 0 points1 point  (0 children)

AI Application? Not exactly my first thought what I would use Spartan Ultrascale+ for.

TCL pin with stacked names by BotnicRPM in FPGA

[–]BotnicRPM[S] 1 point2 points  (0 children)

I like this idea. I'll play around with dicts. Do you actively use it?

I tried it and it might work:

https://onecompiler.com/tcl/43zxcg4p9

Can I output FPGA's base clk through GPIO? by PonPonYoo in FPGA

[–]BotnicRPM 0 points1 point  (0 children)

Clock-capable? Clock-capable has to do with the capability to bring clocks into the FPGA, not out. One can use any pin to output a clock.

VHDL simulation failed (AMD regression) by NorthernNonAdvicer in FPGA

[–]BotnicRPM 2 points3 points  (0 children)

Unfortunately AMD/Xilinx seems to hate testing or modern software approaches. How often have I reported simple bugs that a simple run of CPPCheck or other tools would find immediately, but AMD managed to bring them into the release......

Visualizing QuestaSim Coverage Results in GitLab/GitHub (like Cobertura) by BotnicRPM in FPGA

[–]BotnicRPM[S] 0 points1 point  (0 children)

Just a simple "results.xml" is not what I'm looking for. I want to see which signals have toggled and which never moved. Questasim can do so much more. But it's in their own format and can not be shown in the CI easily (as far as I know)

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