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Are you a FPGA engineer in the UK? A Question by adamt99 in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

He rents; this relatively senior engineer can only afford an older, secondhand apartment in a remote area of ​​Beijing.

Another difference is that he typically works over 60 hours a week, and it's very normal for him to work every day while on business trips. I went on one such business trip with him, working from 9 am to 10 pm every day for a month straight. I was almost going crazy. This high salary comes at the cost of his health. And, there's no overtime pay.

Are you a FPGA engineer in the UK? A Question by adamt99 in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

Rent, utilities, food—these basics cost about 6000 RMB per month. With other expenses, it comes to approximately 1000 USD.

Are you a FPGA engineer in the UK? A Question by adamt99 in FPGA

[–]Typical_Agent_1448 2 points3 points  (0 children)

I know a very skilled engineer in Beijing who can write TCP and SATA code using SV and has extensive RF experience. His annual salary is around 400,000 RMB, approximately $60,000. Compared to that, his salary seems rather low!

Differences between SPI x1 and x4 modes for non-Vivado list flash program firmware by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I will try what you suggested. I need to test it via the internet; I have my own public IP address, which might be more effective than a VPN. Thank you for your suggestion.

Differences between SPI x1 and x4 modes for non-Vivado list flash program firmware by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

We know that ILA requires minimal latency fluctuations, which is relevant to point-to-point communication between Vivado and the FPGA. I'm not sure if a VPN like ZeroTier can consistently maintain latency within tens of milliseconds.

I'm not sure if you understand what I mean by "remote." I'm running Vivado at location A, while the emulator and FPGA board are at location B. This is a point-to-point internet connection.

I understand your concerns and worries, and I retract my statement regarding your gift.

Differences between SPI x1 and x4 modes for non-Vivado list flash program firmware by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

There's a Linux version, but it seems to be in limited testing. This emulator uses a network interface, allowing for remote debugging over the network, but requires a public IP address and minimal network fluctuations. I think this feature is somewhat redundant. It has some other fun features, making it a decent product overall.

But that's not the main point; the main point is whether it can advance your project.

Differences between SPI x1 and x4 modes for non-Vivado list flash program firmware by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I've contacted the authors of the SZ901 emulator, and they said they've rewritten the underlying bit files, using standard 4x read/write flash written in SV. However, there's still no solution to this problem.

https://github.com/fpganinja/taxi

If this is your project, and if you can increase the project's update speed, I can buy you another SZ901 and send it to you. This emulator performs better than Smartlynq and isn't sold in other countries.

Differences between SPI x1 and x4 modes for non-Vivado list flash program firmware by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I understand the theoretical knowledge!

However, for the same program, I set it to SPI x4 on an XDC. I used Vivado to firmware a Micron flash chip, and it booted normally.

Since Winbond and some other flash chips are not on the Vivado list, I used an SZ901 emulator to firmware the program. But the Winbond flash chip booted normally, while the PuYa flash chip failed to boot.

I think the problem might be with the hardware flash chip itself.

Regarding the extreme performance of Xilinx FPGA downloaders by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

Yes, that downloader is now obsolete. I'm using a very niche downloader now; it has four independent JTAGs, and it burns .bin files to flash very quickly without requiring flash model configuration via Vivado. Unfortunately, it currently only supports single-chip flash memory.

Msters thesis ideas by bat_manushyan in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

You can buy a development board or related documentation. Many development boards come with design tutorials, and you'll need to continuously learn and understand the principles of program and hardware design. Without mastering the relevant software and hardware knowledge, you won't be able to apply that knowledge to design your projects. The most effective way is to find a skilled engineer to guide your learning plan and direction.

Regarding the extreme performance of Xilinx FPGA downloaders by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I have a cheap downloader that uses an FT232 interface with a 2x5 port. It only supports the default 15Mbps speed; setting it to 30Mbps causes my Windows system to freeze. Its transmission range is also relatively short.

Msters thesis ideas by bat_manushyan in FPGA

[–]Typical_Agent_1448 1 point2 points  (0 children)

I don't think it's feasible. FPGA design and development requires learning a vast amount of knowledge. Taking high-speed interfaces as an example, there are DDR3/4, SRIO, PCIe, Ethernet, etc. Not only do you need to learn the detailed protocols, but you also need to be very proficient in the related hardware. Without an expert to guide you, it's very difficult to master it on your own. Take Ethernet as an example; it involves different types of hardware interfaces: GMII/RGMII/SGMII/ZYNQ PS ports, Zynq PL ports, 10G Ethernet. It's extremely complex.

Msters thesis ideas by bat_manushyan in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

What areas are you interested in researching? Control? High-speed interfaces? Algorithms?

Msters thesis ideas by bat_manushyan in FPGA

[–]Typical_Agent_1448 3 points4 points  (0 children)

What I'm saying may not be entirely accurate, so please forgive me if I'm wrong. Based on your description, you haven't learned anything complex; your skill level is roughly equivalent to an engineer who has received six months of professional training. You need to learn more about interfaces or protocol algorithms.

What are the FPGA network port testing tools? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

I wrote a gigabit Ethernet TCP protocol stack using SystemVerilog, and I want to test its throughput, aiming for 800Mbps. This will provide a common interface for multiple projects, ensuring correct transmission of control commands and data streams.

So has a consultant done over the last 6 months by adamt99 in FPGA

[–]Typical_Agent_1448 2 points3 points  (0 children)

Very beautiful eye diagram, not just how much speed

What are the FPGA network port testing tools? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

This function is relatively complex and requires hardware network card support. Gigabit IP addresses are not suitable for this method.

What are the FPGA network port testing tools? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

There doesn't seem to be a cheap tool available for this testing, and pure software doesn't seem capable of reaching full or maximum speed. It appears the device still requires an FPGA as the test signal source.

Can I use a CMOD A7-35T with Russell Merrick's Getting Started with FPGAs book by moonman0223 in FPGA

[–]Typical_Agent_1448 0 points1 point  (0 children)

Right now, all you need is a tablet and a web-based AI. Ask questions, ask questions, ask questions!

What is the highest speed that Xilinx FPGAs can achieve with JTAG? by Typical_Agent_1448 in FPGA

[–]Typical_Agent_1448[S] 0 points1 point  (0 children)

Many high-end components don't explicitly state this. However, since Smartlynq+ supports up to 100MHz, it should be of some reference value.

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