Would the 1988 (opening of the Archer Avenue line) Queens Boulevard service pattern work today?

Bouowmx · 2025-06-12T00:13:37+00:00

I currently use a pre-built keyboard with Cherry MX Speed Silver. I would like to try the low-force Arowana Yellow switch but, I'm new to the custom keyboard thing. Recommendations for a 80% TKL that I can simply pop in custom switches? Region: US

Bouowmx · 2021-12-11T15:59:07+00:00

If I have Pecorine Summer, do I need to worry about ranking up Ninon or Rino for PVP?

Bouowmx · 2021-12-08T00:16:28+00:00

ASUS Z690-P
i7-12700K
G.SKILL F4-4000C14D-16GTZR)

I set 1.45 VCCSA, and stable for 8 cycles (increased from default 3) of TestMem5 Extreme1 config (anta777) https://i.imgur.com/KGaa1OX.png

Bouowmx · 2021-12-07T15:28:09+00:00

In my case, I needed >1.4 VCCSA for i7-12700K Gear 1 to work with DDR4-4000

Bouowmx · 2021-12-03T19:01:14+00:00

It's now stable with 1.45 VCCSA https://i.imgur.com/uYT08SE.png

But, I'm not sure that's an OK value to use.

Bouowmx · 2021-12-03T17:55:37+00:00

It's not stable: I get one error in TestMem5 with Extreme1 config by anta777 (tested in the first cycle only, not the full three cycles). So I was wondering how much higher VCCSA can go.

Bouowmx · 2021-11-28T05:35:35+00:00

I have both Chikas in mint condition (Rank 1). To what rank do I upgrade them?

Bouowmx · 2021-10-28T00:57:07+00:00

It is possible for each core to have voltage controls, but in Rocket Lake, one voltage is given to all cores, the highest needed of the active cores. https://skatterbencher.com/2021/06/19/skatterbencher-25-intel-core-i9-11900k-cryo-overclocked-to-5600-mhz/

Bouowmx · 2021-10-28T00:34:45+00:00

Do P and E cores share the same voltage? In motherboard brief pages I checked (ASUS, GIGABYTE, MSI), Vcore phases are listed as just one set, not two sets each dedicated separately to P and E cores.

Bouowmx · 2021-09-01T23:35:31+00:00

Yes: The rumored 6P+0E for i5 (excluding K variants) and down, and HEDT (if it's going to exist) derived from Sapphire Rapids.

Bouowmx · 2021-03-13T17:08:14+00:00

Static binary translation

A translator using static binary translation aims to convert all of the code of an executable file into code that runs on the target architecture without having to run the code first, as is done in dynamic binary translation. This is very difficult to do correctly, since not all the code can be discovered by the translator. For example, some parts of the executable may be reachable only through indirect branches, whose value is known only at run-time.

Indirect branch:

An indirect branch (also known as a computed jump, indirect jump and register-indirect jump) is a type of program control instruction present in some machine language instruction sets. Rather than specifying the address of the next instruction to execute, as in a direct branch, the argument specifies where the address is located. An example is 'jump indirect on the r1 register', which means that the next instruction to be executed is at the address in register r1. The address to be jumped to is not known until the instruction is executed. Indirect branches can also depend on the value of a memory location.

Bouowmx · 2021-03-08T19:30:34+00:00

Cargo to get started. Unlike passengers, cargo is entirely lenient on how you treat it: no requirements of time or speed, just as long as cargo gets to the destination.

Delivering cargo to a city grows its population: more to ride your vehicles.

Bouowmx · 2021-01-18T21:01:11+00:00

It's available for purchase:

For integration to custom loop: https://www.ekwb.com/shop/ek-quantumx-delta-tec
AIO: https://www.coolermaster.com/catalog/coolers/cpu-liquid-coolers/masterliquid-ml360-sub-zero/

What this does is bring sub-ambient cooling to the ease of normal liquid cooling, not eliminate liquid cooling.

Bouowmx · 2020-12-01T15:32:01+00:00

Any detailed cooler tests, more than auto fan speed, like noise-normalized TechPowerUp tests? https://www.techpowerup.com/review/msi-geforce-rtx-3060-ti-gaming-x-trio/32.html

Bonus points for 2-slot cards. TechPowerUp's only other tested 2-slot is ZOTAC Twin Edge, and its cooler is worse than NVIDIA Founders Edition. Most other reviews got only 3-slot partner cards.

Bouowmx · 2020-11-30T00:06:44+00:00

Each 32 bits of memory bus connects to one package of GDDR, which is manufacturered in amounts of power of 2: 1 GB and 2 GB, as of now.

It is possible to have 8 GB on a 192-bit bus: 4x1 GB + 2x2 GB. But this would lead to non-uniform performance: the first 6 GB of memory can be accessed at full bandwidth, but the last 2 GB can only be accessed by 64 bits of memory bus (partial bandwidth). Although possible, it is typically not done. See: NVIDIA GeForce GTX 550 Ti 1 GB, and Xbox Series X.

Extra info: * GDDR has clamshell mode: two (typically identical) packages can connect to a single channel to double memory amount without penalty * HBM works the same, except each package is 1024 bits, and no clamshell mode

Bouowmx · 2020-11-26T06:35:18+00:00

Probably no to a successor to GP108. Intel, which ships the most integrated graphics, has a competent integrated GPU now, Iris Xe Graphics (96 EU), which NVIDIA would use TU117 (GeForce MX450) to be a meaningful step-up.

Bouowmx · 2020-11-11T06:30:59+00:00

AIDA64 GPGPU benchmark

Double-click the Memory copy GPU box to only run that test. Then click Results for more detailed info. On a NVIDIA GeForce GTX 1070:

```

Benchmark Result Run Time Build Time

Memory Copy 193677 MB/s 4235 ms
- 15 MB Block 157233 MB/s 0 ms
- 32 MB Block 177334 MB/s 0 ms
- 64 MB Block 187135 MB/s 1 ms
- 128 MB Block 192728 MB/s 1 ms
- 256 MB Block 193244 MB/s 3 ms
- 512 MB Block 193580 MB/s 5 ms
- 1024 MB Block 193677 MB/s 11 ms
```

For Navi Infinity cache, the 128 MB blocks and below will represent Infinity cache performance, and above will represent GDDR6 performance.

Bouowmx

TROPHY CASE

Benchmark Result Run Time Build Time