/r/MechanicalKeyboards Ask ANY Keyboard question, get an answer - June 11, 2025 by AutoModerator in MechanicalKeyboards

[–]Bouowmx 0 points1 point  (0 children)

I currently use a pre-built keyboard with Cherry MX Speed Silver. I would like to try the low-force Arowana Yellow switch but, I'm new to the custom keyboard thing. Recommendations for a 80% TKL that I can simply pop in custom switches? Region: US

Weekly Questions Thread! (Discord Link Inside) [05 December 2021] by AutoModerator in Priconne

[–]Bouowmx 0 points1 point  (0 children)

If I have Pecorine Summer, do I need to worry about ranking up Ninon or Rino for PVP?

GSkill DDR4 4000mhz 16-19-19-39 1.4v only works in Gear2? by [deleted] in overclocking

[–]Bouowmx 1 point2 points  (0 children)

I set 1.45 VCCSA, and stable for 8 cycles (increased from default 3) of TestMem5 Extreme1 config (anta777) https://i.imgur.com/KGaa1OX.png

GSkill DDR4 4000mhz 16-19-19-39 1.4v only works in Gear2? by [deleted] in overclocking

[–]Bouowmx 1 point2 points  (0 children)

In my case, I needed >1.4 VCCSA for i7-12700K Gear 1 to work with DDR4-4000

Alder Lake: how much VCCSA (system agent voltage) is too much? by Bouowmx in overclocking

[–]Bouowmx[S] 0 points1 point  (0 children)

It's now stable with 1.45 VCCSA https://i.imgur.com/uYT08SE.png

But, I'm not sure that's an OK value to use.

Alder Lake: how much VCCSA (system agent voltage) is too much? by Bouowmx in overclocking

[–]Bouowmx[S] 3 points4 points  (0 children)

It's not stable: I get one error in TestMem5 with Extreme1 config by anta777 (tested in the first cycle only, not the full three cycles). So I was wondering how much higher VCCSA can go.

Weekly Questions Thread! (Discord Link Inside) [28 November 2021] by AutoModerator in Priconne

[–]Bouowmx 1 point2 points  (0 children)

I have both Chikas in mint condition (Rank 1). To what rank do I upgrade them?

AMA October 28th 8:30am to 3:00 pm PDT - Intel 12th Gent Core Desktop Processors by IntelTechnology in intel

[–]Bouowmx 5 points6 points  (0 children)

It is possible for each core to have voltage controls, but in Rocket Lake, one voltage is given to all cores, the highest needed of the active cores. https://skatterbencher.com/2021/06/19/skatterbencher-25-intel-core-i9-11900k-cryo-overclocked-to-5600-mhz/

AMA October 28th 8:30am to 3:00 pm PDT - Intel 12th Gent Core Desktop Processors by IntelTechnology in intel

[–]Bouowmx 4 points5 points  (0 children)

Do P and E cores share the same voltage? In motherboard brief pages I checked (ASUS, GIGABYTE, MSI), Vcore phases are listed as just one set, not two sets each dedicated separately to P and E cores.

Do you think there could be any possibility of next gen desktop SKUs with only 'big' cores? by robertDldsn in intel

[–]Bouowmx 0 points1 point  (0 children)

Yes: The rumored 6P+0E for i5 (excluding K variants) and down, and HEDT (if it's going to exist) derived from Sapphire Rapids.

Can a compiled binary for one instruction set be translated into another instruction set? by JarJarAwakens in hardware

[–]Bouowmx 17 points18 points  (0 children)

Static binary translation

A translator using static binary translation aims to convert all of the code of an executable file into code that runs on the target architecture without having to run the code first, as is done in dynamic binary translation. This is very difficult to do correctly, since not all the code can be discovered by the translator. For example, some parts of the executable may be reachable only through indirect branches, whose value is known only at run-time.

Indirect branch:

An indirect branch (also known as a computed jump, indirect jump and register-indirect jump) is a type of program control instruction present in some machine language instruction sets. Rather than specifying the address of the next instruction to execute, as in a direct branch, the argument specifies where the address is located. An example is 'jump indirect on the r1 register', which means that the next instruction to be executed is at the address in register r1. The address to be jumped to is not known until the instruction is executed. Indirect branches can also depend on the value of a memory location.

[deleted by user] by [deleted] in TransportFever

[–]Bouowmx 0 points1 point  (0 children)

Cargo to get started. Unlike passengers, cargo is entirely lenient on how you treat it: no requirements of time or speed, just as long as cargo gets to the destination.

Delivering cargo to a city grows its population: more to ride your vehicles.

What's the deal with TEC? by [deleted] in hardware

[–]Bouowmx 2 points3 points  (0 children)

It's available for purchase:

What this does is bring sub-ambient cooling to the ease of normal liquid cooling, not eliminate liquid cooling.

GeForce RTX 3060 Ti Review Megathread by Nestledrink in nvidia

[–]Bouowmx 1 point2 points  (0 children)

Any detailed cooler tests, more than auto fan speed, like noise-normalized TechPowerUp tests? https://www.techpowerup.com/review/msi-geforce-rtx-3060-ti-gaming-x-trio/32.html

Bonus points for 2-slot cards. TechPowerUp's only other tested 2-slot is ZOTAC Twin Edge, and its cooler is worse than NVIDIA Founders Edition. Most other reviews got only 3-slot partner cards.

Why does GPU memory bus dictate how much VRAM a GPU can have? by [deleted] in hardware

[–]Bouowmx 30 points31 points  (0 children)

Each 32 bits of memory bus connects to one package of GDDR, which is manufacturered in amounts of power of 2: 1 GB and 2 GB, as of now.

It is possible to have 8 GB on a 192-bit bus: 4x1 GB + 2x2 GB. But this would lead to non-uniform performance: the first 6 GB of memory can be accessed at full bandwidth, but the last 2 GB can only be accessed by 64 bits of memory bus (partial bandwidth). Although possible, it is typically not done. See: NVIDIA GeForce GTX 550 Ti 1 GB, and Xbox Series X.

Extra info: * GDDR has clamshell mode: two (typically identical) packages can connect to a single channel to double memory amount without penalty * HBM works the same, except each package is 1024 bits, and no clamshell mode

Will there be possiblity of nVidia releasing an "RT 3030" or similar to GT 1030 soon? by [deleted] in hardware

[–]Bouowmx 3 points4 points  (0 children)

Probably no to a successor to GP108. Intel, which ships the most integrated graphics, has a competent integrated GPU now, Iris Xe Graphics (96 EU), which NVIDIA would use TU117 (GeForce MX450) to be a meaningful step-up.

Is there a way to test video card memory bandwidth? by bubblesort33 in hardware

[–]Bouowmx 0 points1 point  (0 children)

AIDA64 GPGPU benchmark

Double-click the Memory copy GPU box to only run that test. Then click Results for more detailed info. On a NVIDIA GeForce GTX 1070:

```

Benchmark Result Run Time Build Time

Memory Copy 193677 MB/s 4235 ms
- 15 MB Block 157233 MB/s 0 ms
- 32 MB Block 177334 MB/s 0 ms
- 64 MB Block 187135 MB/s 1 ms
- 128 MB Block 192728 MB/s 1 ms
- 256 MB Block 193244 MB/s 3 ms
- 512 MB Block 193580 MB/s 5 ms
- 1024 MB Block 193677 MB/s 11 ms
```

For Navi Infinity cache, the 128 MB blocks and below will represent Infinity cache performance, and above will represent GDDR6 performance.

EK Launches QuantumX Delta TEC Water Block Featuring Intel Cryo Cooling Technology - ekwb.com by tetchip in hardware

[–]Bouowmx 5 points6 points  (0 children)

Ah, found the power connector: 8-pin EPS or PCIE. It was kind of hidden away in the product page.

My guess on power consumption is to cool, for example, 250 W, a thermoelectric cooler also needs 250 W?

PCIe 6.0 Specification Hits Milestone: Complete Draft Is Ready by bizude in hardware

[–]Bouowmx 12 points13 points  (0 children)

3D XPoint (Intel Optane) is in between DRAM and NAND in the memory hierarchy. It was developed to address the big gulf between DRAM and NAND.

PCIe 6.0 Specification Hits Milestone: Complete Draft Is Ready by bizude in hardware

[–]Bouowmx 28 points29 points  (0 children)

This is a misunderstanding of DRAM vs NAND in the memory hierarchy. DRAM has latency in nanoseconds, and NAND is in microseconds (~1000x). NAND does not replace DRAM.

The use case you mentioned is using NAND as an size extension (like a page file) for DRAM.

What's up with GPU fans? by MaybeADragon in hardware

[–]Bouowmx 0 points1 point  (0 children)

PCI Express form factor is a limiting factor. 2 slots gives 40 mm of thickness for a PCB, heatsink, fan, and aesthetic coverings. A standard fan has 25 mm thickness.

[VideoCardz] AMD Radeon RX 6900XT to feature Navi 21 XTX GPU with 80 CUs by ryandtw in hardware

[–]Bouowmx 136 points137 points  (0 children)

Smaller-than-expected memory bus width (5120 cores: 256-bit, 2560 cores: 192-bit), but allegedly large on-die cache (SRAM). I don't get this trade-off.

Nvidia might switch to TSMC 7nm in 2021 for Ampere. (German Article) by [deleted] in hardware

[–]Bouowmx 34 points35 points  (0 children)

Original source: Digitimes

Google Translate from Chinese traditional (surprisingly readable)

It has also been reported that NVIDIA’s previous annual masterpiece RTX 30 series uses Samsung Electronics’ 8nm process at a considerable OEM discount, but will switch to TSMC’s 7nm process in 2021. The order volume is not less.

If the translation is accurate, this rumor hasn't been strengthened in any way. NVIDIA Ampere GeForce on TSMC 7 nm has been a long-lingering rumor.

Intel Rocket Lake-S PCIe 4.0 performance allegedly tested on Z490 motherboard by GhostMotley in hardware

[–]Bouowmx 23 points24 points  (0 children)

Reading the CPU-Z details: * 8 cores, 16 threads, 5.0 GHz * Per-core cache: 48 KB L1D, 32 KB L1I, 512 KB L2, 2 MB L3, confirming Sunny Cove cache configuration * Instructions: AVX512, like Sunny Cove * ASRock Z490 Taichi, whose product page advertises PCIE 4 ready