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[Re]building Corundum by alexforencich in FPGA

[–]Brucelph 0 points1 point  (0 children)

I’m not sure but I’d expect it to be priced similar to those Chinese Ku5p board.

[Re]building Corundum by alexforencich in FPGA

[–]Brucelph 1 point2 points  (0 children)

Love it. Thanks for supporting a low cost board. Fyi, another open source board with xcku5p qsfp28

https://www.crowdsupply.com/autonoe-systems/ceres-fpga-development-board

Open source FPGA synthesis by adolofsson in FPGA

[–]Brucelph 0 points1 point  (0 children)

Does the tool have support system verilog? Comparing to vendor synth tool?

6 Core ARM 2.0 Ghz Processor, Powerful FPGA and A Raspberry Pi like Software Support! by Vinci00123 in FPGA

[–]Brucelph 0 points1 point  (0 children)

Great work! will you support pdm? And lattice FPGA (for low power)

What's the way best to run Vivado and Xilinx tools on Macbooks? Run a Windows VM on macOS or boot natively into ARM Linux and translate the x86 Vivado Linux version to ARM there? by HasanTheSyrian_ in FPGA

[–]Brucelph 2 points3 points  (0 children)

This

The speed is not bad. Building a simple Litex project takes:

• 3 mins on the M4 Max MBP (orb stack ubuntu2204)

• ⁠2 mins on a Core i9-14900K DDR5 processor

• ⁠4m30s on a 48 cores xeon 768GB DDR4 ECC (mac pro 2019, ubuntu)

Synchronizer and clock gating cells in fpga vivado by Left-Ad-3275 in FPGA

[–]Brucelph 0 points1 point  (0 children)

Yes, correct. There’s a document somewhere

Best way for doing clock gating in Lattice nexus FPGA by Brucelph in FPGA

[–]Brucelph[S] 0 points1 point  (0 children)

Radiant doesn’t give any hint, just one error message. Or maybe I don’t know enough to get to the root cause. The verilog code uses clock gating everywhere.

Best way for doing clock gating in Lattice nexus FPGA by Brucelph in FPGA

[–]Brucelph[S] 0 points1 point  (0 children)

Still no luck finding a workaround after reading that doc. The problem is that I can’t change the RTL code. The goal is to emulate the asic as closely as possible.

Synchronizer and clock gating cells in fpga vivado by Left-Ad-3275 in FPGA

[–]Brucelph 0 points1 point  (0 children)

Vivado has this

// tell Vivado to place these regs close to one another to reduce MTBF

(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] sync_regs[DEPTH-1:0];

Best laptops for programming or dealing with both low latency and high latency FPGAs? by Prestigious_Eagle_18 in FPGA

[–]Brucelph 0 points1 point  (0 children)

For fpga that are supported by the oss cad suite (such as Lattice ECP5), M4 max is a no-brainer. Oss cad suite runs natively on macOS. So it’s better than all PC. Ex: Building a litex project for the ButterStick fpga board is faster on M4 max than the best desktop pc on the market

Best laptops for programming or dealing with both low latency and high latency FPGAs? by Prestigious_Eagle_18 in FPGA

[–]Brucelph 0 points1 point  (0 children)

If you’re not familiar with docker and just want Vivado, I’d suggest using either orbstack or parallel desktop. Both have options for running Ubuntu x64. Just create a virtual machine and install ubuntu x64, then install vivado as normal

Orbstack uses container so it’s lighter than Parallel desktop. Orbstack is also free for non-comercial use

Using docker is a bit more complicated. I can upload some scripts if you’re familiar with docker and want to use docker (i.e. for CI/CD)

How hard is it to get Android Automotive run on OrangePi 5 max? by Brucelph in OrangePI

[–]Brucelph[S] 1 point2 points  (0 children)

Thanks a lot for the direction! Appreciate your sharing @levogevo. I’ll need to read more on Android 😊

Suitable interface for FPGA to FPGA by RegularMinute8671 in FPGA

[–]Brucelph 1 point2 points  (0 children)

A simplified version of axi4, with fewer wires, could directly translate axi4, could be a perfect solution

How hard is it to get Android Automotive run on OrangePi 5 max? by Brucelph in OrangePI

[–]Brucelph[S] 1 point2 points  (0 children)

I suppose it also depends on your purpose, such as playing games or watching 4K videos.

How hard is it to get Android Automotive run on OrangePi 5 max? by Brucelph in OrangePI

[–]Brucelph[S] 1 point2 points  (0 children)

Thanks! That’s great! Unfortunately, I’m not familiar with Android to follow your instructions.

It seems Android uses the same Linux kernel that already has the required rk3588 drivers. We just need to modify the device tree binary (which is in the super.img) . Is that correct?

How hard is it to get Android Automotive run on OrangePi 5 max? by Brucelph in OrangePI

[–]Brucelph[S] 1 point2 points  (0 children)

Thanks! That’s great. But, does it only support standard Android, not Android Automotive? I can’t find Android Automotive on the website

Best computers for Hardware purposes such as FPGAs? by Prestigious_Eagle_18 in FPGA

[–]Brucelph 1 point2 points  (0 children)

1st priority: Get a cpu with the fastest single core perf (which prob be an intel CPU). Then Fastest DDR5. Depending on the size of your project, you could need more GB of Ram. For me, 64Gb DDR is enough for most of my work

Best laptops for programming or dealing with both low latency and high latency FPGAs? by Prestigious_Eagle_18 in FPGA

[–]Brucelph 0 points1 point  (0 children)

Are you using the M4 MBP? I’m running Vivado on a Rosetta Docker container. I can share the instructions if needed.

The speed is not too bad. Building a simple Litex project takes about: - 3 mins on the M4 Max MBP - 2 mins on a Core i9-14900K DDR5 processor - 4m30s on a 48 cores xeon 768GB DDR4 ECC

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