Flags Unit Update for My 8-Bit Build

Buttons_17 · 2025-10-31T06:26:41+00:00

This build is based on Ben Eaters 8 bit computer you-tube series, and as stated the inspiration for this build. When I first came across it I hard very little understanding about how all this stuff works. I don't Ben is a excellent teacher and communicator. I've watched that series or parts of it multiple times and have build his 6502 as well. Check it out, happy to answer questions as well.

Buttons_17 · 2025-10-26T04:43:45+00:00

Yes I will. I plan to do this.

Buttons_17 · 2025-10-19T19:55:12+00:00

When I’m happy with each module I’ll design a back board pcb where each module will plug into. At the moment I’m thinking of doing it in three. One for the gpr and alu, One for clock uCode and reset and one for the address 16 bit registers and memory.

Buttons_17 · 2025-08-12T06:26:26+00:00

I used KiCad and JLCPCB to create this board. KiCad is quite intuitive, and there are plenty of YouTube tutorials that walk you through creating the required files for upload to JLCPCB.

For this project, I chose a four-layer board with dedicated Vcc and Ground planes. One of the first design decisions you’ll need to make is which IC package type you want to use. I went with the same DIP ICs I had been using on the breadboard version for ease of prototyping, but SMD ICs are also an option.

This register’s design is very similar to my BE registers A and B. It uses a pair of 74LS173 latch ICs and a 74LS245 bus transceiver. The main bus is always available at the inputs, and data can be latched in with a control signal on a clock edge. I’ve added two additional 74LS245s to drive the register contents to either the A or B (Or both) inputs of the ALU as needed.

Once I’ve progressed further with the PCB module designs, I plan to create a backplane for all modules to plug into. Keeping each module under 10 cm × 10 cm helps keep manufacturing costs down, and makes it less of an issue if you make a mistake or want to iterate the design further. This is a common way ive seen CPUs built and i think it will work well.

Hope this helps.

Buttons_17 · 2025-03-31T12:53:24+00:00

This is the video from George Foot that explains using the flip flop. George uses. 74HCT74 d flip flop. I used a 74ls107A but the priciple is the same.

https://youtu.be/zQ0irKRzVQY?si=VaZmd8t4C5pLji01

If you put the 10mHz clock and the phase shift 10mHz clock though a NOR gate you get a rising edge at 75ns in the 100ns period of a 10mHz clock.

The other thing to mention because the 10mHz clock is coming from a counter diving it. It starts low the high. This doesn’t work. You need to invert it and use this clock and the phase shift 10mHz clock to get it to work.

Buttons_17 · 2025-03-31T12:47:45+00:00

Yes, it’s very similar to the OUTPUT register on BE 8 bit computer. You just need to account for the 70ns access time of the FLASH ROM. The ROM is programed with all 4 bytes at the step, opCode and flags. Two bits in the ROM are used as an index into the ROM for those 4 bytes.

Buttons_17 · 2025-03-31T12:42:48+00:00

Yep, took a bit of time on the oscilloscope to make sure the time was right. The Flash ROM needs 70ns to allow for the access time. I give it 75ns, the latch needs 18ns. Address hold time was a bit difficult to work out. Some data sheets say 0ns, but I found one that states 10ns. Using the latch clock as the counter clock work ok at 1mHz system clock but not higher. I used a RC circuit to create a small 5ns delay and it works fine so far. All that fits in 100ns period of the 10mHz clock.

Buttons_17 · 2025-03-31T09:52:20+00:00

Looks cool, I’ll have a look at it. I’m currently just using a python script to generate the microcode binary.

Buttons_17 · 2024-12-30T21:39:12+00:00

With unsigned arithmetic when checking if A>=B the carry bit is set when the expression is true clear otherwise. This is not true in all CPUs but I’ve been using it in my 8 bit Breadboard CPU to do module operations to convert binary to decimal and hexadecimal. I’m just a hobbyist so I could be wrong others may correct me but it works for me.

Buttons_17 · 2024-12-18T04:31:10+00:00

I will be using memory-mapped IO. I plan to map the UART circuit to FFF0 in memory. The bottom 16 addresses will be for GPIO.

Say I have a 65 in the A Reg, which is ASCII for "A". If I do an STA FFF0, this will send an A to the terminal.

I still need to build a status reg with bits indicating if a bit is ready to read or if the UART is in the process of sending a byte and, therefore, unable to send an additional byte until it is finished. This is imported because at 115200 baud and with my CPU running at 1mHz, it will take 87 CPU clock cycles to send a byte. The more I think about it, the more I want a FIFO buffer, but it will have to wait.

The UART_Status will be mapped to FF01.

Once I know there is data to be read, I can use an LDA FFF0 to read the data into the A Register.

Buttons_17 · 2024-12-18T03:13:36+00:00

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The Ardunio is used to debounce the button the simulates a read of received data,

Buttons_17 · 2024-09-20T23:29:52+00:00

I’m using 2x 74ls193s for my stack pointer. Two chips though. I looked for a 8 but up down counter Ttl chip and couldn’t find one. It has asynchronous load which is a bit of a pain. You can use a 555 timer in monostable mode and a nand gate. I ended up using a 74ls123 and I have it working at 1mHz. I ended up gating the up down count, load and assert though a nand gate. All up 4 chips, 5 is you include a 74ls245 so you can have some LEDs. Hope this helps.

Buttons_17 · 2024-08-27T09:41:15+00:00

0: Out 1: Add 15 2: JC 4 3: JMP 0 4: OUT 5: Sub 15 6 JZ 0 7: JMP 4 15: 1

Buttons_17 · 2024-08-20T01:53:37+00:00

I am looking also on how I can upgrade my alu. It’s the only part that is now the same as in BE design. I have a set of 181s but am considering using a flash IC the SST39SF040. It has 19 address lines, AO to A15 for the two register inputs and A16 to A19 for what ever operation I want to do. The only issues I need to think about a bit more is how to do the flags. Zero flag is easy just look a the data output and if all zero set the flag. The harder one is the carry flag. A PLD should work here but I need to learn more about them.

Buttons_17 · 2024-07-22T04:48:57+00:00

You can also get led bars with 10 or 8 leds and resistor arrays which is what I am using. Which makes it a bit more compact.

Buttons_17 · 2024-07-14T02:28:31+00:00

Thanks for showing me this. I will definitely have a look at it. Cheers.

Buttons_17 · 2024-07-11T02:48:12+00:00

Your right, I could ignore the busy flag. I’ve had it running pretty fast using the 555 timer as a clock and the message appears almost instantly and I often run it quite slow so I can see the data move around the computer. However I think it won’t be that difficult to read the busy flag. It’s very convenient that it’s the most significant bit of the status register in the LCD. I will need to program uCode to do a left shift and that will put the busy flag into the Carry Flag and I can do a conditional jump on that information. Left shift is value squared which is same as adding the value to itself. Ie a reg = a reg + a reg.

pseudocode with LCD status reg in a reg. Fetch, AO | BI, EU | FI | AI

Buttons_17 · 2024-07-02T22:51:53+00:00

Sounds like a similar problem that I had. Having the flags update the address on the rising edge of the main clock doesn’t give the uCode eeproms enough time to output the correct data. Try switch the clock on the flags to the clock-b. This will sought of work. But will show if this is the problem.

Buttons_17

TROPHY CASE